PWM_extend
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5326KB
下载次数：23
上传日期：2011-05-03 16:10:14
上 传 者：
2285898
说明： 本代码采用RTL级的硬件描述语言设计了一个多通道的PWM波形捕获、输出模块。主要用在无人机或是其它需要控制多个伺候电机的场合。开发环境为Xilinx公司的ISE12.0。
(This code uses RTL-level hardware description language designed a multi-channel PWM waveform capture, output module. Mainly used in the need to control multiple unmanned aerial vehicles or other places serve the motor. Xilinx development environment for the company' s ISE12.0.)
文件列表:
PWM_extend\clk.cmd_log (3086, 2010-10-26)
PWM_extend\clk.lso (6, 2010-09-08)
PWM_extend\clk.prj (22, 2010-10-26)
PWM_extend\clk.spl (121, 2010-10-26)
PWM_extend\clk.stx (1172, 2010-10-26)
PWM_extend\clk.sym (1839, 2010-10-26)
PWM_extend\clk.symbak (1843, 2010-10-26)
PWM_extend\clk.symcmd (56, 2010-09-15)
PWM_extend\clk.v (2158, 2010-10-26)
PWM_extend\clk.xst (215, 2010-10-26)
PWM_extend\clk_beh.prj (83, 2010-09-09)
PWM_extend\clk_stx_beh.prj (93, 2010-09-09)
PWM_extend\counter_16.cmd_log (626, 2010-10-27)
PWM_extend\counter_16.lso (6, 2010-09-13)
PWM_extend\counter_16.prj (29, 2010-09-13)
PWM_extend\counter_16.spl (99, 2010-10-27)
PWM_extend\counter_16.stx (1355, 2010-09-13)
PWM_extend\counter_16.sym (1393, 2010-10-27)
PWM_extend\counter_16.v (969, 2010-09-15)
PWM_extend\counter_16.xst (271, 2010-09-13)
PWM_extend\counter_24.cmd_log (1250, 2010-10-28)
PWM_extend\counter_24.lso (6, 2010-09-13)
PWM_extend\counter_24.prj (29, 2010-09-13)
PWM_extend\counter_24.spl (99, 2010-10-28)
PWM_extend\counter_24.stx (1250, 2010-09-13)
PWM_extend\counter_24.sym (1393, 2010-10-28)
PWM_extend\counter_24.v (986, 2010-07-27)
PWM_extend\counter_24.xst (271, 2010-09-13)
PWM_extend\fuse.log (2143, 2011-04-25)
PWM_extend\Half_freq.cmd_log (308, 2010-09-15)
PWM_extend\Half_freq.spl (91, 2010-09-15)
PWM_extend\Half_freq.sym (1112, 2010-09-15)
PWM_extend\Half_freq.v (251, 2010-05-27)
PWM_extend\hostlistfile.txt (20, 2010-11-11)
PWM_extend\ipcore_dir\clk_ip_DCM.v (6044, 2010-09-20)
PWM_extend\ipcore_dir\clk_ip_DCM.xaw (4830, 2010-09-20)
PWM_extend\ipcore_dir\clk_ip_DCM_arwz.ucf (1338, 2010-09-20)
PWM_extend\ipcore_dir\clk_ip_DCM_flist.txt (107, 2010-09-20)
PWM_extend\ipcore_dir\clk_ip_DCM_xmdf.tcl (1708, 2010-09-20)
... ...
The following files were generated for 'clk_ip_DCM' in directory
D:\PWM_ISE\PWM_UART_0917\PWM_extend\ipcore_dir\
clk_ip_DCM_readme.txt:
Text file indicating the files generated and how they are used.
clk_ip_DCM_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
clk_ip_DCM_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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