TEST
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：526KB
下载次数：5
上传日期：2011-05-03 19:19:31
上 传 者：
happy_cui
说明： I2C总线的实现，一个基于计数器的加法器。其中使用三个寄存器来实现计数器的功能，再由两个半半加器实现全加器额功能。
(realize the inter-integrated circuit bus )
文件列表:
TEST (0, 2011-04-24)
TEST\.lso (6, 2011-04-21)
TEST\adder1.vhd (1328, 2011-04-21)
TEST\ADDER_8.vhd (2038, 2011-04-21)
TEST\CounterA.vhd (1542, 2011-04-21)
TEST\CounterA_vhdl.prj (43, 2011-04-21)
TEST\CounterB.v (632, 2011-04-21)
TEST\CounterB.vhd (1623, 2011-04-21)
TEST\CounterB_vhdl.prj (43, 2011-04-21)
TEST\CounterC.vhd (1434, 2011-04-23)
TEST\CounterC_vhdl.prj (43, 2011-04-21)
TEST\halfadd.vhd (1093, 2011-04-21)
TEST\halfadd_vhdl.prj (42, 2011-04-21)
TEST\I2C.cmd_log (138, 2011-04-24)
TEST\I2C.lso (6, 2011-04-24)
TEST\I2C.ngc (23962, 2011-04-24)
TEST\I2C.ngr (32547, 2011-04-24)
TEST\I2C.prj (197, 2011-04-24)
TEST\I2C.spl (59, 2011-04-21)
TEST\I2C.stx (0, 2011-04-24)
TEST\I2C.sym (806, 2011-04-21)
TEST\I2C.syr (19342, 2011-04-24)
TEST\I2C.vhd (1949, 2011-04-23)
TEST\I2C.xst (1131, 2011-04-24)
TEST\I2C_summary.html (3521, 2011-04-24)
TEST\I2C_vhdl.prj (261, 2011-04-24)
TEST\isim (0, 2011-04-24)
TEST\isim.cmd (14, 2011-04-24)
TEST\isim.hdlsourcefiles (125, 2011-04-24)
TEST\isim.log (1127, 2011-04-24)
TEST\isim.tmp_save (0, 2011-04-24)
TEST\isim.tmp_save\_1 (7006, 2011-04-24)
TEST\isimwavedata.xwv (31956, 2011-04-24)
TEST\isim\file graph (0, 2011-04-23)
TEST\isim\temp (0, 2011-04-24)
TEST\isim\temp\hdllib.ref (1134, 2011-04-24)
TEST\isim\temp\hdpdeps.ref (3032, 2011-04-24)
TEST\isim\temp\sub00 (0, 2011-04-24)
TEST\isim\temp\sub00\vhpl00.vho (808, 2011-04-24)
TEST\isim\temp\sub00\vhpl01.vho (753, 2011-04-24)
... ...
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