文件列表:

VERILOG\DDR_8TO1_16CHAN_TX.v (23291, 2006-05-25)
VERILOG\RESOURCE_SHARING_CONTROL.v (5630, 2006-05-24)
VERILOG\BIT_ALIGN_MACHINE.v (15262, 2006-07-18)
VERILOG\DDR_8TO1_16CHAN_RX.v (40660, 2006-09-07)
VERILOG (0, 2006-09-07)
VHDL\BIT_ALIGN_MACHINE.vhd (23664, 2006-09-19)
VHDL\count_to_128.vhd (3163, 2006-08-15)
VHDL\count_to_16x.vhd (2949, 2006-09-07)
VHDL\COUNT_TO_64.vhd (3465, 2006-09-07)
VHDL\DDR_8TO1_16CHAN_RX.vhd (71656, 2006-09-07)
VHDL\DDR_8TO1_16CHAN_TX.vhd (36384, 2006-09-06)
VHDL\RESOURCE_SHARING_CONTROL.vhd (8758, 2006-07-25)
VHDL\seven_bit_reg_w_ce.vhd (3336, 2006-07-25)
VHDL (0, 2006-09-07)

******************************************************************************* ** Copyright (c) 2006 Xilinx, Inc. ** All Rights Reserved ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: readme.txt ** / / Timestamp: 7 Sep 2006 ** /___/ /\ ** \ \ / \ ** \___\/\___\ ** ** ** Device: Virtex-5 ** Purpose: ** Readme file for contents of XAPP855.ZIP. These files are associated with ** the 16 Channel DDR LVDS Interface reference design outlined in XAPP855. ** 1. Implementation details: ** a. Synthesis/Place & Route software used to develop ** reference design. Specific software settings also mentioned here ** if appropriate. ** b. Platform used for hardware verification testing ** 2. Source code file descriptions ** 3. Build-related support file descriptions ** 4. General notes (if appropriate) ** ** Reference: ** XAPP855 ** Revision History: ** Rev 1.0 - First created, GBurton, 9/7/06 ** ** ******************************************************************************* ******************************************************************************* ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement,or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrantor ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits,cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright 2006 Xilinx, Inc. ** All rights reserved ** ******************************************************************************* ******************************************************************************* ** Implementation Details ******************************************************************************* HDL Language(s) - VHDL/Verilog Synthesis - XST, ISE 8.2i SP3 (I.34) Place/Route: - ISE 8.2i SP3 (I.34) Hardware Verification: Platform - ML550 Networking Interfaces Board Target Part - XC5VLX50T-FF1136 (all speed grades) Target Bus Width - 16-bit Target Bus Clock Speed - 800, 900, 1000 Mb/s (-1, -2, -3) ******************************************************************************* ** File Descriptions and Design Hierarchy ******************************************************************************* The xapp855.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \Verilog - Verilog design files \VHDL - VHDL Design files **************************************** ** HDL design files **************************************** Design Hierarchy for XAPP855 Reference Design NOTE: All file extentions are .vhd or .v 1. DDR_8TO1_16CHAN_TX 2. DDR_8TO1_16CHAN_RX a. RESOURCE_SHARING_CONTROL i. COUNT_TO_128 ii. COUNT_TO_16X b. BIT_ALIGN_MACHINE i. COUNT_TO_128 ii. SEVEN_BIT_REG_W_CE c. COUNT_TO_***

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