axi_ad9361
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：40KB
下载次数：69
上传日期：2018-01-18 21:01:45
上 传 者：
大木瓜
说明： AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现
(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
文件列表:
axi_ad9361\axi_ad9361.cache\wt\java_command_handlers.wdf (154, 2017-02-06)
axi_ad9361\axi_ad9361.cache\wt\webtalk_pa.xml (1415, 2017-02-06)
axi_ad9361\axi_ad9361.v (15462, 2016-08-02)
axi_ad9361\axi_ad9361.xpr (12388, 2017-02-06)
axi_ad9361\axi_ad9361_alt_lvds_rx.v (7082, 2016-08-02)
axi_ad9361\axi_ad9361_alt_lvds_tx.v (6289, 2016-08-02)
axi_ad9361\axi_ad9361_constr.xdc (2145, 2016-08-02)
axi_ad9361\axi_ad9361_dev_if.v (14608, 2016-08-02)
axi_ad9361\axi_ad9361_dev_if_alt.v (9684, 2016-08-02)
axi_ad9361\axi_ad9361_hw.tcl (8934, 2016-08-02)
axi_ad9361\axi_ad9361_ip.tcl (1837, 2016-08-02)
axi_ad9361\axi_ad9361_rx.v (11552, 2016-08-02)
axi_ad9361\axi_ad9361_rx_channel.v (8372, 2016-08-02)
axi_ad9361\axi_ad9361_rx_pnmon.v (12295, 2016-08-02)
axi_ad9361\axi_ad9361_tdd.v (11296, 2016-08-02)
axi_ad9361\axi_ad9361_tdd_if.v (4484, 2016-08-02)
axi_ad9361\axi_ad9361_tx.v (11317, 2016-08-02)
axi_ad9361\axi_ad9361_tx_channel.v (14897, 2016-08-02)
axi_ad9361\component.xml (83622, 2017-09-11)
axi_ad9361\Makefile (2174, 2016-08-02)
axi_ad9361\xgui\axi_ad9361_v1_0.tcl (4796, 2017-09-11)
axi_ad9361\axi_ad9361.cache\wt (0, 2017-11-04)
axi_ad9361\axi_ad9361.cache (0, 2017-11-04)
axi_ad9361\xgui (0, 2017-11-04)
axi_ad9361 (0, 2017-11-04)
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