ethernet_interface_20160424_A
所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:24616KB
下载次数:7
上传日期:2018-02-26 14:42:25
上 传 者:
knifesxl
说明: 基于Xilinx Spartan-6开发板,实现以太网通信
(Ethernet communication)
文件列表:
ethernet_interface (0, 2016-04-24)
ethernet_interface\.Xil (0, 2016-03-08)
ethernet_interface\chipscope (0, 2016-04-24)
ethernet_interface\chipscope\coregen.cgp (239, 2016-01-12)
ethernet_interface\chipscope\coregen.log (2430, 2016-01-12)
ethernet_interface\chipscope\create_icon.tcl (1332, 2016-01-12)
ethernet_interface\chipscope\create_ila.tcl (1335, 2016-01-12)
ethernet_interface\chipscope\ethernet_top.cdc (619, 2016-01-12)
ethernet_interface\chipscope\icon.asy (183, 2016-01-12)
ethernet_interface\chipscope\icon.constraints (0, 2016-03-06)
ethernet_interface\chipscope\icon.constraints\icon.ucf (375, 2016-01-12)
ethernet_interface\chipscope\icon.constraints\icon.xdc (793, 2016-01-12)
ethernet_interface\chipscope\icon.gise (2490, 2016-04-24)
ethernet_interface\chipscope\icon.ncf (0, 2016-04-24)
ethernet_interface\chipscope\icon.ngc (31979, 2016-01-12)
ethernet_interface\chipscope\icon.sym (605, 2016-01-12)
ethernet_interface\chipscope\icon.ucf (375, 2016-01-12)
ethernet_interface\chipscope\icon.v (872, 2016-01-12)
ethernet_interface\chipscope\icon.veo (1063, 2016-01-12)
ethernet_interface\chipscope\icon.xco (1658, 2016-01-12)
ethernet_interface\chipscope\icon.xdc (793, 2016-01-12)
ethernet_interface\chipscope\icon.xise (4872, 2016-04-24)
ethernet_interface\chipscope\icon_flist.txt (261, 2016-01-12)
ethernet_interface\chipscope\icon_xmdf.tcl (3131, 2016-01-12)
ethernet_interface\chipscope\ila.asy (343, 2016-01-12)
ethernet_interface\chipscope\ila.cdc (7061, 2016-01-12)
ethernet_interface\chipscope\ila.constraints (0, 2016-03-06)
ethernet_interface\chipscope\ila.constraints\ila.ucf (400, 2016-01-12)
ethernet_interface\chipscope\ila.constraints\ila.xdc (477, 2016-01-12)
ethernet_interface\chipscope\ila.gise (2489, 2016-04-24)
ethernet_interface\chipscope\ila.ncf (0, 2016-04-24)
ethernet_interface\chipscope\ila.ngc (662968, 2016-01-12)
ethernet_interface\chipscope\ila.sym (1036, 2016-01-12)
ethernet_interface\chipscope\ila.ucf (400, 2016-01-12)
ethernet_interface\chipscope\ila.v (926, 2016-01-12)
ethernet_interface\chipscope\ila.veo (1119, 2016-01-12)
ethernet_interface\chipscope\ila.xco (4384, 2016-01-12)
ethernet_interface\chipscope\ila.xdc (477, 2016-01-12)
ethernet_interface\chipscope\ila.xise (4866, 2016-04-24)
... ...
The following files were generated for 'ila' in directory
E:\yc\ethernet_interface\chipscope\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* ila.cdc
* ila.constraints/ila.ucf
* ila.constraints/ila.xdc
* ila.ncf
* ila.ngc
* ila.ucf
* ila.v
* ila.veo
* ila.xdc
* ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* ila.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* ila.sym
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* ila.gise
* ila.xise
Deliver Readme:
Readme file for the IP.
* ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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