eetop.cn_利用FPGA实现浮点运算的verilog代码
所属分类：VHDL/FPGA/Verilog
开发工具：Quartus II
文件大小：127KB
下载次数：24
上传日期：2018-03-12 14:35:14
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说明： 计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。
浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.1024×10^4，也就是 .1024e+004，3.1415926就能表示成0.31415926×10^1，也就是 .31415926e+001，这就是浮点数。浮点数进行的运算就是浮点运算。
浮点运算比常规运算更复杂，因此计算机进行浮点运算速度要比进行常规运算慢得多。
(Floating point representation is a bit like scientific notation (*.***** * 10^***), its representation is 0.***** * 10^*** in the computer in the form of.***** e +, * * *) in front of the asterisk represents fixed-point decimal, which is part of the 0 pure decimal integer index, part of the back is a fixed integer. In this way, any integer and decimal can be expressed. For example, 1024 can be expressed as 0.1024 * 10^4, that is,.1024e+004, 3.1415926 can be expressed as 0.31415926 * 10^1, that is.31415926e+001, that is the floating point number. The operation of floating-point numbers is floating point operation.)
文件列表:
fpu\fpu.pdf (48166, 2005-02-13)
fpu\浮点运算简介.htm (23252, 2005-07-24)
fpu\fcmp\fcmp.v (6578, 2005-02-13)
fpu\fcmp\test_top.v (7474, 2005-02-13)
fpu\fcmp (0, 2006-11-07)
fpu\sourse\except.v (4895, 2005-02-13)
fpu\sourse\fpu.v (17825, 2005-02-13)
fpu\sourse\post_norm.v (24168, 2005-02-13)
fpu\sourse\pre_norm.v (9411, 2005-02-13)
fpu\sourse\pre_norm_fmul.v (5530, 2005-02-13)
fpu\sourse\primitives.v (3348, 2005-02-13)
fpu\sourse (0, 2006-11-07)
fpu\test_bench\sel_test.vh (23503, 2005-02-13)
fpu\test_bench\test_top.v (9854, 2005-02-13)
fpu\test_bench (0, 2006-11-07)
fpu\浮点运算简介.files\back.gif (49, 2005-07-24)
fpu\浮点运算简介.files\css.css (248, 2005-07-24)
fpu\浮点运算简介.files\Thumbs.db (3072, 2006-11-06)
fpu\浮点运算简介.files (0, 2006-11-07)
fpu\fpu.tar.tar (74177, 2006-12-08)
fpu (0, 2006-11-07)
FPU Notes
---------
1) The FPU will never generate a SNAN output
1a) The SNAN output is asserted when one of the operands
was a signaling NAN (output will be a quiet NAN).
1b) The QNAN output is asserted whenever the OUTPUT of
the FPU is NAN (always a quiet NAN).
FPU
===
The FPU consists of the following files:
verilog/fpu.v
verilog/pre_norm.v
verilog/primitives.v
verilog/post_norm.v
verilog/except.v",
verilog/pre_norm_fmul.v
(fpu.v is the top level)
The testbench is in: test_bench/test_top.v
To simulate the FPU using the included test bench
use a comand like:
verilog test_bench/test_top.v \
verilog/fpu.v \
verilog/pre_norm.v \
verilog/primitives.v \
verilog/post_norm.v \
verilog/except.v \
verilog/pre_norm_fmul.v
FCMP
====
The FP compare consists of
fcmp/verilog/fcmp.v
The testbench for FP compare is in: fcmp/test_bench/test_top.v
To simulate the FP compare using the included test bench
use a comand like:
verilog fcmp/test_bench/test_top.v \
fcmp/verilog/fcmp.v
MISC
====
Do not change the directory structure, the testbench
depends on it !
Please also read the README file in the test_vectors
directory.
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