ECG_ADS
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：1461KB
下载次数：21
上传日期：2018-03-13 21:00:13
上 传 者：
blt
说明： ads8684四路通道采样驱动程序，并且有简单的注释说明，能够根据需要修改模拟信号的采样范围
(ads8684 drivers(verilog))
文件列表:
ECG_ADS\ads8684.v (2674, 2017-12-28)
ECG_ADS\ads8684_config.cmd_log (118, 2017-12-28)
ECG_ADS\ads8684_config.lso (6, 2017-12-28)
ECG_ADS\ads8684_config.prj (33, 2017-12-28)
ECG_ADS\ads8684_config.syr (5349, 2017-12-28)
ECG_ADS\ads8684_config.v (5322, 2017-12-28)
ECG_ADS\ads8684_config.xst (1113, 2017-12-28)
ECG_ADS\ads8684_config_xst.xrpt (9005, 2017-12-28)
ECG_ADS\auto_project.ipf (21119, 2018-02-01)
ECG_ADS\ECG_ADS.gise (17689, 2018-01-04)
ECG_ADS\ecg_ads.ucf (358, 2017-12-27)
ECG_ADS\ECG_ADS.xise (38962, 2017-12-28)
ECG_ADS\fuse.xmsgs (367, 2018-01-02)
ECG_ADS\fuseRelaunch.cmd (233, 2018-01-02)
ECG_ADS\impact.xsl (1477, 2018-03-11)
ECG_ADS\impact_impact.xwbt (199, 2018-03-11)
ECG_ADS\ipcore_dir\clock\doc\clk_wiz_v3_6_vinfo.html (6789, 2017-12-27)
ECG_ADS\ipcore_dir\clock\doc\pg065_clk_wiz.pdf (42657, 2017-12-27)
ECG_ADS\ipcore_dir\clock\example_design\clock_exdes.ucf (2619, 2017-12-27)
ECG_ADS\ipcore_dir\clock\example_design\clock_exdes.v (5844, 2017-12-27)
ECG_ADS\ipcore_dir\clock\example_design\clock_exdes.xdc (3111, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\implement.bat (3610, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\implement.sh (3489, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_ise.bat (2695, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_ise.sh (2603, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_ise.tcl (3074, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_rdn.bat (2690, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_rdn.sh (2595, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\planAhead_rdn.tcl (3176, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\xst.prj (74, 2017-12-27)
ECG_ADS\ipcore_dir\clock\implement\xst.scr (165, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\clock_tb.v (4751, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simcmds.tcl (141, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simulate_isim.bat (2744, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simulate_isim.sh (2625, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simulate_mti.bat (2747, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simulate_mti.do (2662, 2017-12-27)
ECG_ADS\ipcore_dir\clock\simulation\functional\simulate_mti.sh (2617, 2017-12-27)
... ...
The following files were generated for 'ila' in directory
F:\Projects\Xilinx\ADS8684\ipcore_dir\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* ila.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* ila.cdc
* ila.constraints/ila.ucf
* ila.constraints/ila.xdc
* ila.ncf
* ila.ngc
* ila.ucf
* ila.v
* ila.veo
* ila.xdc
* ila_xmdf.tcl
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* ila.asy
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* ila.sym
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* ila.gise
* ila.xise
Deliver Readme:
Readme file for the IP.
* ila_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* ila_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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