08_ethernet_1g
所属分类：VHDL/FPGA/Verilog
开发工具：Vivado
文件大小：15884KB
下载次数：4
上传日期：2018-03-16 10:43:02
上 传 者：
kang24
说明： Artix7 XC7A100T芯片控制千兆PHY的二层通信，源代码
(Artix7 XC7A100T chip control Gigabit PHY two layer communication, source code)
文件列表:
08_ethernet_1g (0, 2018-03-02)
08_ethernet_1g\ethernet_test (0, 2018-03-02)
08_ethernet_1g\ethernet_test\.Xil (0, 2018-03-02)
08_ethernet_1g\ethernet_test\.Xil\Vivado-18848-LAOLUO-PC (0, 2018-03-02)
08_ethernet_1g\ethernet_test\.Xil\Vivado-18848-LAOLUO-PC\wave (0, 2017-01-14)
08_ethernet_1g\ethernet_test\constrs_1 (0, 2018-03-02)
08_ethernet_1g\ethernet_test\constrs_1\new (0, 2018-03-02)
08_ethernet_1g\ethernet_test\constrs_1\new\ethernet.xdc (22612, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\activehdl (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\ies (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\modelsim (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\questa (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\riviera (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\compile_simlib\vcs (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt\java_command_handlers.wdf (543, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt\project.wpc (123, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt\synthesis.wdf (3757, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt\synthesis_details.wdf (100, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.cache\wt\webtalk_pa.xml (1610, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.hw\ethernet_test.lpr (343, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\hw_1 (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.hw\hw_1\hw.xml (685, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\hw_1\wave (0, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\webtalk (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.hw\webtalk\.xsim_webtallk.info (59, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\webtalk\labtool_webtalk.log (407, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\webtalk\usage_statistics_ext_labtool.html (4138, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.hw\webtalk\usage_statistics_ext_labtool.xml (3814, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ip (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ipstatic (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ipstatic\blk_mem_gen_v8_3_1 (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ipstatic\blk_mem_gen_v8_3_1\simulation (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ipstatic\blk_mem_gen_v8_3_1\simulation\blk_mem_gen_v8_3.vhd (222214, 2017-01-14)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ip\ram (0, 2018-03-02)
08_ethernet_1g\ethernet_test\ethernet_test.ip_user_files\ip\ram\ram.veo (3127, 2017-01-14)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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