Final_final_test
所属分类：Windows编程
开发工具：Verilog
文件大小：4547KB
下载次数：15
上传日期：2018-04-02 19:24:34
上 传 者：
接触的小茄子
说明： 五级流水CPU设计
流水线是数字系统中一种提高系统稳定性和工作速度的方法，广泛应用于高档CPU的架构中。根据MIPS处理器的特点，将整体的处理过程分为取指令（IF）、指令译码（ID）、执行（EX）、存储器访问（MEM）和寄存器会写（WB）五级，对应多周期的五个处理阶段。一个指令的执行需要5个时钟周期，每个时钟周期的上升沿来临时，此指令所代表的一系列数据和控制信息将转移到下一级处理。
(Five level flow CPU design)
文件列表:
Final_final_test\ALU.v (345, 2017-12-05)
Final_final_test\ControlUnit.v (918, 2017-11-13)
Final_final_test\DtoE.v (1211, 2017-12-06)
Final_final_test\EqualD.v (149, 2017-12-06)
Final_final_test\EtoM.v (697, 2017-12-06)
Final_final_test\FtoD.v (377, 2017-12-06)
Final_final_test\HazardUnit.v (1164, 2017-12-06)
Final_final_test\modelsim.ini (11129, 2017-12-06)
Final_final_test\MtoW.v (601, 2017-12-06)
Final_final_test\mywork\@a@l@u\verilog.prw (230, 2017-12-06)
Final_final_test\mywork\@a@l@u\verilog.psm (4664, 2017-12-06)
Final_final_test\mywork\@a@l@u\_primary.dat (427, 2017-12-06)
Final_final_test\mywork\@a@l@u\_primary.dbs (472, 2017-12-06)
Final_final_test\mywork\@a@l@u\_primary.vhd (333, 2017-12-06)
Final_final_test\mywork\@control@unit\verilog.prw (825, 2017-12-06)
Final_final_test\mywork\@control@unit\verilog.psm (13376, 2017-12-06)
Final_final_test\mywork\@control@unit\_primary.dat (1324, 2017-12-06)
Final_final_test\mywork\@control@unit\_primary.dbs (1803, 2017-12-06)
Final_final_test\mywork\@control@unit\_primary.vhd (628, 2017-12-06)
Final_final_test\mywork\@dto@e\verilog.prw (691, 2017-12-06)
Final_final_test\mywork\@dto@e\verilog.psm (16872, 2017-12-06)
Final_final_test\mywork\@dto@e\_primary.dat (1193, 2017-12-06)
Final_final_test\mywork\@dto@e\_primary.dbs (1872, 2017-12-06)
Final_final_test\mywork\@dto@e\_primary.vhd (1517, 2017-12-06)
Final_final_test\mywork\@dto@m\verilog.prw (443, 2017-12-06)
Final_final_test\mywork\@dto@m\verilog.psm (7816, 2017-12-06)
Final_final_test\mywork\@dto@m\_primary.dat (535, 2017-12-06)
Final_final_test\mywork\@dto@m\_primary.dbs (892, 2017-12-06)
Final_final_test\mywork\@dto@m\_primary.vhd (761, 2017-12-06)
Final_final_test\mywork\@equal@d\verilog.prw (191, 2017-12-06)
Final_final_test\mywork\@equal@d\verilog.psm (2696, 2017-12-06)
Final_final_test\mywork\@equal@d\_primary.dat (230, 2017-12-06)
Final_final_test\mywork\@equal@d\_primary.dbs (365, 2017-12-06)
Final_final_test\mywork\@equal@d\_primary.vhd (257, 2017-12-06)
Final_final_test\mywork\@eto@m\verilog.prw (480, 2017-12-06)
Final_final_test\mywork\@eto@m\verilog.psm (9424, 2017-12-06)
Final_final_test\mywork\@eto@m\_primary.dat (668, 2017-12-06)
Final_final_test\mywork\@eto@m\_primary.dbs (1092, 2017-12-06)
Final_final_test\mywork\@eto@m\_primary.vhd (804, 2017-12-06)
Final_final_test\mywork\@fto@d\verilog.prw (290, 2017-12-06)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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