C5G_LPDDR2_RTL_Test
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：2257KB
下载次数：5
上传日期：2018-04-03 13:07:14
上 传 者：
和禾
说明： LPDDR2工程，alteral的c5芯片，板子上验证过，可以直接用。
(LPDDR2 project, alteral's C5 chip, has been verified on board and can be directly used.)
文件列表:
C5G_LPDDR2_RTL_Test (0, 2018-04-03)
C5G_LPDDR2_RTL_Test\Avalon_bus_RW_Test.v (4991, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.cdf (332, 2018-04-03)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.done (26, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.fit.smsg (1028, 2013-08-08)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.fit.summary (723, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.jdi (4901, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.map.smsg (3328, 2014-05-15)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.map.summary (547, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.pin (79475, 2014-06-23)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.pti_db_list.ddb (296, 2014-05-20)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.qpf (118, 2013-08-07)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.qsf (109085, 2018-04-03)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.qws (367, 2018-04-03)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.sdc (3650, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.sof (4001404, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.sta.summary (15485, 2014-06-24)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.tis_db_list.ddb (296, 2014-05-20)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test.v (12549, 2014-06-23)
C5G_LPDDR2_RTL_Test\C5G_LPDDR2_RTL_Test_assignment_defaults.qdf (47533, 2014-05-15)
C5G_LPDDR2_RTL_Test\c5_pin_model_dump.txt (3697, 2013-08-07)
C5G_LPDDR2_RTL_Test\db (0, 2018-04-03)
C5G_LPDDR2_RTL_Test\db\C5G_LPDDR2_RTL_Test.db_info (144, 2018-04-03)
C5G_LPDDR2_RTL_Test\db\C5G_LPDDR2_RTL_Test.sld_design_entry.sci (1474, 2018-04-03)
C5G_LPDDR2_RTL_Test\db\stp1_auto_stripped.stp (175076, 2018-04-03)
C5G_LPDDR2_RTL_Test\demo_batch (0, 2018-04-03)
C5G_LPDDR2_RTL_Test\demo_batch\C5G_LPDDR2_RTL_Test.bat (433, 2013-08-07)
C5G_LPDDR2_RTL_Test\demo_batch\C5G_LPDDR2_RTL_Test.sof (4001404, 2014-06-24)
C5G_LPDDR2_RTL_Test\fpga_lpddr2 (0, 2018-04-03)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.bsf (19168, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.cmp (4723, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.ppf (3333, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.qip (15391, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.sip (12914, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.spd (9475, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2.v (32186, 2014-06-23)
C5G_LPDDR2_RTL_Test\fpga_lpddr2\altdq_dqs2_acv_connect_to_hard_phy_cyclonev_lpddr2.sv (59666, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2\altera_avalon_mm_bridge.v (11619, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2\altera_avalon_sc_fifo.v (34467, 2014-05-15)
C5G_LPDDR2_RTL_Test\fpga_lpddr2\altera_avalon_st_pipeline_base.v (4705, 2014-05-15)
... ...
The simulation example design is available for both Verilog and VHDL.
To generate the Verilog example design, open the Quartus project "generate_sim_example_design.qpf" and
select Tools -> Tcl Scripts... -> generate_sim_verilog_example_design.tcl and click "Run".
Alternatively, you can run "quartus_sh -t generate_sim_verilog_example_design.tcl"
at a Windows or Linux command prompt.
The generated files will be found in the subdirectory "verilog".
To generate the VHDL example design, open the Quartus project "generate_sim_example_design.qpf" and
select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".
Alternatively, you can run "quartus_sh -t generate_sim_vhdl_example_design.tcl"
at a Windows or Linux command prompt.
The generated files will be found in the subdirectory "vhdl".
To simulate the example design using Modelsim AE/SE:
1) Move into the directory ./verilog/mentor or ./vhdl/mentor
2) Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".
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