apb

所属分类:Windows编程
开发工具:Verilog
文件大小:1KB
下载次数:1
上传日期:2018-04-10 12:40:35
上 传 者朱al
说明:  当定时器控制寄存器EX_CON的CNT_START信号为1时,32位定时器开始计数 ü 当计数值等于定时时间配置寄存器EX_TO,定时器变为0,此时定时器控制寄存 器EX_CON的INT_EN为1,OVFL_CLS信号为0时,定时器中断信号INT_B变为低 电平 ü 当定时器控制寄存器EX_CON的OVFL_CLS信号为1时,NT_B变为高电平
(When the CNT_START signal of timer control register EX_CON is 1, the 32 bit timer starts counting. U when the count value is equal to the time variable configuration register EX_TO, timer 0, timer control register at When the INT_EN of the EX_CON is 1 and the OVFL_CLS signal is 0, the timer interrupt signal INT_B becomes low. level U OVFL_CLS signal when the timer control register EX_CON is 1, NT_B becomes high level)

文件列表:
apb\APB_BUS_tb_zhulv.v (837, 2017-07-18)
apb\APB_BUS_zhulv.v (2342, 2017-07-13)
apb (0, 2018-04-10)

近期下载者

相关文件


收藏者