verilog2vhdl
所属分类：其他
开发工具：LINUX
文件大小：22858KB
下载次数：1
上传日期：2018-04-18 18:44:07
上 传 者：
nosova
说明： Verilog2C++ translates a C++ class of a Verilog design using a cycle-accurate representation of each nets and registers. Verilog2C++ is about 10 times faster than other commercial simulators, but has only simple functions.
文件列表:
verilog2vhdl (0, 2013-04-11)
verilog2vhdl\11APR2013 (0, 2013-02-10)
verilog2vhdl\11APR2013\bin (0, 2013-03-09)
verilog2vhdl\11APR2013\bin\verilog2vhdl (1012, 2013-02-13)
verilog2vhdl\11APR2013\bin\verilog2vhdl.bat (863, 2013-02-08)
verilog2vhdl\11APR2013\bin\verilog2vhdlcomponent (1028, 2013-02-13)
verilog2vhdl\11APR2013\bin\verilog2vhdlcomponent.bat (863, 2013-02-08)
verilog2vhdl\11APR2013\bin\verilog2vhdlentity (1023, 2013-02-13)
verilog2vhdl\11APR2013\bin\verilog2vhdlentity.bat (876, 2013-02-08)
verilog2vhdl\11APR2013\examples (0, 2012-02-04)
verilog2vhdl\11APR2013\examples\simple_and (0, 2012-12-23)
verilog2vhdl\11APR2013\examples\simple_and\runme.bat (69, 2012-12-01)
verilog2vhdl\11APR2013\examples\simple_and\runme.csh (84, 2012-11-30)
verilog2vhdl\11APR2013\examples\simple_and\simple_and.v (804, 2012-02-04)
verilog2vhdl\11APR2013\lib (0, 2013-02-10)
verilog2vhdl\11APR2013\lib\designplayer.jar (24014332, 2013-04-11)
verilog2vhdl\11APR2013\LICENSE.txt (1424, 2013-02-09)
verilog2vhdl\11APR2013\setup_env.bat (183, 2013-02-13)
verilog2vhdl\11APR2013\setup_env.csh (800, 2013-02-13)
verilog2vhdl\11APR2013\setup_env.sh (825, 2013-02-13)
verilog2vhdl\11APR2013\vhdl_pkgs (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex\body.dmp (219395, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_complex\math_complex.dmp (49871, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real\body.dmp (137863, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\math_real\math_real.dmp (29820, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit\body.dmp (345296, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_bit\numeric_bit.dmp (63299, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std\body.dmp (515667, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\numeric_std\numeric_std.dmp (98095, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164 (0, 2013-02-10)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164\body.dmp (172202, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_1164\std_logic_1164.dmp (37673, 2013-04-06)
verilog2vhdl\11APR2013\vhdl_pkgs\lib\ieee\std_logic_arith (0, 2013-02-10)
... ...
**************************************************************************
* *
* Verilog To VHDL Converter *
* Copyright (C) 2012, edautils.com *
* *
**************************************************************************
Welcome to this free Verilog To VHDL Converter!
This utility is meant for those users who wants to convert
their Verilog design into VHDL . This utility has been implemented in
Java and packaged as a JAR file. Goto installation area and source
the setup_env file to setup the environment for this tool.
You need to execute this utility as -
verilog2vhdl -in simple_and.v -top simple_and -out output.vhd
OR
java com.eu.miscedautils.verilog2vhdl.verilog2vhdl -in simple_and.v -top simple_and -out output.vhd
There are options like -only_entity to create just only the entity.
Also, there are options like -only_component a component
declaration corresponding to the specified top module.
FYI- you need Java 1.6.x or above to run this utility.
See the example(s) to understand the usage better.
For any assistance contact help@edautils.com .
FEEDBACK
========
Send feedback to help@edautils.com
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