文件列表:

QSPI (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\EWARM (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\EWARM\Project.ewd (41688, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\EWARM\Project.ewp (30141, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\EWARM\Project.eww (161, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\EWARM\startup_stm32f746xx.s (29123, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\EWARM\stm32f746xx_flash.icf (1908, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Inc (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\Inc\main.h (8666, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Inc\stm32f7xx_hal_conf.h (16621, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Inc\stm32f7xx_it.h (3157, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\MDK-ARM (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\MDK-ARM\Project.uvoptx (19858, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\MDK-ARM\Project.uvprojx (22565, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\MDK-ARM\STM32746G-DISCOVERY (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\MDK-ARM\STM32746G-DISCOVERY\STM32746G-DISCOVERY.sct (533, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\MDK-ARM\startup_stm32f746xx.s (32638, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\SW4STM32 (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\SW4STM32\STM32746G-DISCOVERY (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\SW4STM32\STM32746G-DISCOVERY\.cproject (11701, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\SW4STM32\STM32746G-DISCOVERY\.project (5232, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\SW4STM32\STM32746G-DISCOVERY\STM32F746NGHx_FLASH.ld (5042, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\SW4STM32\startup_stm32f746xx.s (27566, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Src (0, 2018-04-17)
QSPI\QSPI_ExecuteInPlace\Src\main.c (19272, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Src\stm32f7xx_hal_msp.c (8067, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Src\stm32f7xx_it.c (5807, 2017-12-27)
QSPI\QSPI_ExecuteInPlace\Src\system_stm32f7xx.c (15126, 2017-12-27)
QSPI\QSPI_PreInitConfig (0, 2018-04-17)
QSPI\QSPI_PreInitConfig\EWARM (0, 2018-04-17)
QSPI\QSPI_PreInitConfig\EWARM\Project.ewd (41688, 2017-12-27)
QSPI\QSPI_PreInitConfig\EWARM\Project.ewp (30141, 2017-12-27)
QSPI\QSPI_PreInitConfig\EWARM\Project.eww (161, 2017-12-27)
QSPI\QSPI_PreInitConfig\EWARM\startup_stm32f746xx.s (29123, 2017-12-27)
QSPI\QSPI_PreInitConfig\EWARM\stm32f746xx_flash.icf (1868, 2017-12-27)
QSPI\QSPI_PreInitConfig\Inc (0, 2018-04-17)
QSPI\QSPI_PreInitConfig\Inc\main.h (8665, 2017-12-27)
QSPI\QSPI_PreInitConfig\Inc\stm32f7xx_hal_conf.h (16621, 2017-12-27)
... ...

/** @page QSPI_ReadWrite_IT QSPI Read/Write in interrupt mode example @verbatim ******************** (C) COPYRIGHT 2016 STMicroelectronics ******************* * @file QSPI/QSPI_ReadWrite_IT/readme.txt * @author MCD Application Team * @brief Description of the QSPI Read/Write in interrupt mode example. ****************************************************************************** * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** @endverbatim @par Example Description This example describes how to configure and use QPSI through the STM32F7xx HAL API. This example erases part of the QSPI memory, writes data in IT mode, reads data in IT mode, and compares the result in a forever loop. LED1 is toggled each time a new comparison is successful LED1 is turned on as soon as a comparison error occurs or an error is returned by HAL API In this example, HCLK is configured at 216 MHz. @note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds) based on a variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise, the caller ISR process will be blocked. To change the SysTick interrupt priority you have to use the HAL_NVIC_SetPriority() function. @note The application needs to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation. @par Keywords Memory, QSPI, Erase, Read, Write, Interrupt @NoteIf the user code size exceeds the DTCM-RAM size or starts from internal cacheable memories (SRAM1 and SRAM2),that is shared between several processors, then it is highly recommended to enable the CPU cache and maintain its coherence at application level. In case of constraints it is possible to configure the MPU as "Write through/not shareable" to guarantee the cache coherence at write access but the user has to ensure the cache maintenance at read access though. The address and the size of cacheable buffers (shared between CPU and other masters) must be properly updated to be aligned to cache line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. Even though the user must manage the cache coherence for read accesses. Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs” Please refer to the AN4839 “Level 1 cache on STM32F7 Series” @par Directory contents - QSPI/QSPI_ReadWrite_IT/Inc/stm32f7xx_hal_conf.h HAL configuration file - QSPI/QSPI_ReadWrite_IT/Inc/stm32f7xx_it.h Interrupt handlers header file - QSPI/QSPI_ReadWrite_IT/Inc/main.h Header for main.c module - QSPI/QSPI_ReadWrite_IT/Src/stm32f7xx_it.c Interrupt handlers - QSPI/QSPI_ReadWrite_IT/Src/main.c Main program - QSPI/QSPI_ReadWrite_IT/Src/system_stm32f7xx.c STM32F7xx system source file - QSPI/QSPI_ReadWrite_IT/Src/stm32f7xx_hal_msp.c HAL MSP file @par Hardware and Software environment - This example runs on STM32F7xx devices. - This example has been tested on STM32746G-DISCOVERY board and can be easily tailored to any other supported device and/or development board. - STM32746G-DISCOVERY Set-up : - Board is configured by default to access QSPI memory @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example *

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