clock
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：747KB
下载次数：1
上传日期：2018-05-11 14:31:42
上 传 者：
viod
说明： 12制 24制可切换电子钟，有时分秒，都可校时
(clock can adjust minute,hour,seconds)
文件列表:
clock\clock.cache\wt\gui_resources.wdf (4956, 2018-05-01)
clock\clock.cache\wt\java_command_handlers.wdf (1633, 2018-05-01)
clock\clock.cache\wt\project.wpc (121, 2018-05-01)
clock\clock.cache\wt\synthesis.wdf (5384, 2018-04-30)
clock\clock.cache\wt\synthesis_details.wdf (100, 2018-04-30)
clock\clock.cache\wt\webtalk_pa.xml (5235, 2018-05-01)
clock\clock.hw\clock.lpr (343, 2018-04-30)
clock\clock.hw\hw_1\hw.xml (741, 2018-05-01)
clock\clock.runs\.jobs\vrs_config_1.xml (209, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_10.xml (405, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_11.xml (405, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_2.xml (209, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_3.xml (223, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_4.xml (209, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_5.xml (223, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_6.xml (230, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_7.xml (402, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_8.xml (402, 2018-04-30)
clock\clock.runs\.jobs\vrs_config_9.xml (230, 2018-04-30)
clock\clock.runs\impl_1\.init_design.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.init_design.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.opt_design.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.opt_design.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.place_design.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.place_design.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.route_design.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.route_design.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.vivado.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.vivado.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.Vivado_Implementation.queue.rst (0, 2018-04-30)
clock\clock.runs\impl_1\.write_bitstream.begin.rst (181, 2018-04-30)
clock\clock.runs\impl_1\.write_bitstream.end.rst (0, 2018-04-30)
clock\clock.runs\impl_1\clock.bit (2192113, 2018-04-30)
clock\clock.runs\impl_1\clock.tcl (4751, 2018-04-30)
clock\clock.runs\impl_1\clock.vdi (20399, 2018-04-30)
clock\clock.runs\impl_1\clock_13712.backup.vdi (17804, 2018-04-30)
clock\clock.runs\impl_1\clock_7144.backup.vdi (17825, 2018-04-30)
clock\clock.runs\impl_1\clock_clock_utilization_routed.rpt (14216, 2018-04-30)
clock\clock.runs\impl_1\clock_control_sets_placed.rpt (4164, 2018-04-30)
clock\clock.runs\impl_1\clock_drc_opted.rpt (2227, 2018-04-30)
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