Verilog_Ip_ROM
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：5370KB
下载次数：1
上传日期：2018-06-01 20:15:59
上 传 者：
我欲飞翔
说明： 基于ALTERA芯片来驱动IP核是ROM只读存储器
(IP core driven by ALTERA chip is ROM read-only memory.)
文件列表:
Verilog_Ip_ROM\db\.cmp.kpt (211, 2016-03-23)
Verilog_Ip_ROM\db\altsyncram_kqa1.tdf (9301, 2016-03-23)
Verilog_Ip_ROM\db\altsyncram_nna1.tdf (9283, 2016-03-23)
Verilog_Ip_ROM\db\altsyncram_u024.tdf (19353, 2016-03-23)
Verilog_Ip_ROM\db\altsyncram_v3a1.tdf (9623, 2016-03-23)
Verilog_Ip_ROM\db\cmpr_ngc.tdf (1684, 2016-03-23)
Verilog_Ip_ROM\db\cmpr_qgc.tdf (1916, 2016-03-23)
Verilog_Ip_ROM\db\cmpr_rgc.tdf (2006, 2016-03-23)
Verilog_Ip_ROM\db\cntr_23j.tdf (3298, 2016-03-23)
Verilog_Ip_ROM\db\cntr_cgi.tdf (3733, 2016-03-23)
Verilog_Ip_ROM\db\cntr_egi.tdf (3864, 2016-03-23)
Verilog_Ip_ROM\db\cntr_g9j.tdf (4102, 2016-03-23)
Verilog_Ip_ROM\db\decode_dvf.tdf (1565, 2016-03-23)
Verilog_Ip_ROM\db\logic_util_heursitic.dat (51128, 2016-03-23)
Verilog_Ip_ROM\db\mux_rsc.tdf (4725, 2016-03-23)
Verilog_Ip_ROM\db\prev_cmp_Verilog_Ip_ROM.qmsg (74508, 2016-03-23)
Verilog_Ip_ROM\db\stp1_auto_stripped.stp (23374, 2016-04-21)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(0).cnf.cdb (1289, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(0).cnf.hdb (897, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(1).cnf.cdb (1798, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(1).cnf.hdb (1082, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(10).cnf.cdb (1824, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(10).cnf.hdb (725, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(11).cnf.cdb (2361, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(11).cnf.hdb (1544, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(12).cnf.cdb (5000, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(12).cnf.hdb (857, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(13).cnf.cdb (2992, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(13).cnf.hdb (1889, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(14).cnf.cdb (1586, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(14).cnf.hdb (827, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(15).cnf.cdb (1810, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(15).cnf.hdb (1473, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(16).cnf.cdb (2468, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(16).cnf.hdb (750, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(17).cnf.cdb (10457, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(17).cnf.hdb (2752, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(18).cnf.cdb (2629, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(18).cnf.hdb (762, 2016-03-23)
Verilog_Ip_ROM\db\Verilog_Ip_ROM.(19).cnf.cdb (1981, 2016-03-23)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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