Tarea1
所属分类：VHDL/FPGA/Verilog
开发工具：C/C++
文件大小：25037KB
下载次数：0
上传日期：2018-06-25 22:06:46
上 传 者：
igmesa
说明： Programming of an FPGA to control the switching on and off of lights at the push of a button.
文件列表:
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\0d01a83af7bf1b76.xci (13421, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\system_auto_pc_0.dcp (266235, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\system_auto_pc_0_sim_netlist.v (407573, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\system_auto_pc_0_sim_netlist.vhdl (511073, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\system_auto_pc_0_stub.v (4561, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76\system_auto_pc_0_stub.vhdl (5061, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\0d01a83af7bf1b76.logs\runme.log (17418, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\145ff7164761d71f.xci (182264, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\system_xbar_0.dcp (111282, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\system_xbar_0_sim_netlist.v (119718, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\system_xbar_0_sim_netlist.vhdl (145864, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\system_xbar_0_stub.v (3637, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f\system_xbar_0_stub.vhdl (4202, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\145ff7164761d71f.logs\runme.log (10715, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\ad949dec08aec129.xci (9231, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\system_led_ip_0_0.dcp (37679, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\system_led_ip_0_0_sim_netlist.v (53580, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\system_led_ip_0_0_sim_netlist.vhdl (61662, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\system_led_ip_0_0_stub.v (2419, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129\system_led_ip_0_0_stub.vhdl (2610, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\ad949dec08aec129.logs\runme.log (23610, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\fdd5db6351951680.xci (4888, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\led_ip_0.dcp (37369, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\led_ip_0_sim_netlist.v (53553, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\led_ip_0_sim_netlist.vhdl (61635, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\led_ip_0_stub.v (2401, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680\led_ip_0_stub.vhdl (2592, 2018-04-03)
Tarea_1\Tarea_1.cache\ip\2017.2\fdd5db6351951680.logs\runme.log (23254, 2018-04-03)
Tarea_1\Tarea_1.cache\wt\gui_resources.wdf (12046, 2018-04-16)
Tarea_1\Tarea_1.cache\wt\java_command_handlers.wdf (3431, 2018-04-16)
Tarea_1\Tarea_1.cache\wt\project.wpc (122, 2018-04-16)
Tarea_1\Tarea_1.cache\wt\synthesis.wdf (5402, 2018-04-03)
Tarea_1\Tarea_1.cache\wt\synthesis_details.wdf (100, 2018-04-03)
Tarea_1\Tarea_1.cache\wt\webtalk_pa.xml (10412, 2018-04-16)
Tarea_1\Tarea_1.hw\Tarea_1.lpr (290, 2018-04-03)
Tarea_1\Tarea_1.ip_user_files\bd\system\hdl\system.vhd (111602, 2018-04-03)
Tarea_1\Tarea_1.ip_user_files\bd\system\ip\system_auto_pc_0\sim\system_auto_pc_0.v (12379, 2018-04-03)
Tarea_1\Tarea_1.ip_user_files\bd\system\ip\system_axi_gpio_0_0\sim\system_axi_gpio_0_0.vhd (8749, 2018-03-05)
Tarea_1\Tarea_1.ip_user_files\bd\system\ip\system_axi_gpio_0_0\system_axi_gpio_0_0_sim_netlist.v (54362, 2018-03-05)
Tarea_1\Tarea_1.ip_user_files\bd\system\ip\system_axi_gpio_0_0\system_axi_gpio_0_0_sim_netlist.vhdl (65988, 2018-03-05)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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