Xilinx FPGA高级设计及应用
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：5869KB
下载次数：18
上传日期：2018-06-27 10:57:20
上 传 者：
Jerry_Z
说明： Xilinx FPGA高级设计及应用 （随书附带源码）
(Xilinx FPGA advanced design and application (with the source code included with the book))
文件列表:
Reconfig\1.cpj (10591, 2009-03-23)
Reconfig\11.prm (611, 2009-02-16)
Reconfig\11.sig (223, 2009-02-16)
Reconfig\asy_detector.vhd (1981, 2009-03-21)
Reconfig\asy_fifo.asy (954, 2009-02-09)
Reconfig\asy_fifo.edn (74018, 2009-02-09)
Reconfig\asy_fifo.ngo (28242, 2009-02-11)
Reconfig\asy_fifo.sym (1415, 2009-02-09)
Reconfig\asy_fifo.v (4143, 2009-02-09)
Reconfig\asy_fifo.veo (3072, 2009-02-09)
Reconfig\asy_fifo.vhd (4367, 2009-02-09)
Reconfig\asy_fifo.vho (3816, 2009-02-09)
Reconfig\asy_fifo.xco (1259, 2009-02-09)
Reconfig\asy_fifo_flist.txt (169, 2009-02-09)
Reconfig\automake.log (0, 2009-02-21)
Reconfig\baudrate.bld (576, 2009-02-17)
Reconfig\baudrate.cmd_log (1231, 2009-02-17)
Reconfig\baudrate.lso (6, 2009-02-17)
Reconfig\baudrate.mrp (6572, 2009-02-17)
Reconfig\baudrate.ncd (10917, 2009-02-17)
Reconfig\baudrate.ngc (11339, 2009-02-17)
Reconfig\baudrate.ngd (18551, 2009-02-17)
Reconfig\baudrate.ngm (31856, 2009-02-17)
Reconfig\baudrate.ngr (3992, 2009-02-17)
Reconfig\baudrate.pad (12359, 2009-02-17)
Reconfig\baudrate.par (3452, 2009-02-17)
Reconfig\baudrate.par_nlf (1099, 2009-02-17)
Reconfig\baudrate.pcf (215, 2009-02-17)
Reconfig\baudrate.prj (26, 2009-02-17)
Reconfig\baudrate.stx (0, 2009-02-17)
Reconfig\baudrate.syr (11947, 2009-02-17)
Reconfig\baudrate.twr (2076, 2009-02-17)
Reconfig\baudrate.twx (13783, 2009-02-17)
Reconfig\baudrate.vhd (2147, 2009-03-21)
Reconfig\baudrate.xpi (46, 2009-02-17)
Reconfig\baudrate_last_par.ncd (9718, 2009-02-12)
Reconfig\baudrate_map.ncd (7586, 2009-02-17)
Reconfig\baudrate_map.ngm (31856, 2009-02-17)
Reconfig\baudrate_pad.csv (12391, 2009-02-17)
... ...
The following files were generated for
in directory
G:\wireless\test\fpga_logic\fpga_logic:
asy_fifo.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
asy_fifo.edn:
Electronic Data Netlist (EDN) file containing the information
required to implement the module in a Xilinx (R) FPGA.
asy_fifo.sym:
Please see the core data sheet.
asy_fifo.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
asy_fifo.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
asy_fifo.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
asy_fifo.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
asy_fifo.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
asy_fifo_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
asy_fifo_readme.txt:
Text file indicating the files generated and how they are used.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：