src
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：60KB
下载次数：3
上传日期：2018-08-07 23:44:36
上 传 者：
江山无限辉
说明： 以太网MAC数据链路层，在FPGA内用Verilog语言实现对应功能
(Ethernet MAC layer,in FPGA, implement this function with verilog language)
文件列表:
src\afifo.v (6425, 2008-08-17)
src\clk\CLK_DIV2.v (3598, 2006-10-23)
src\clk\CLK_SWITCH.v (3664, 2006-10-23)
src\clk\duram.v (1523, 2006-10-23)
src\clk_ctrl.v (5246, 2017-11-07)
src\eth_miim.v (16634, 2008-08-17)
src\mac_rx.v (12124, 2017-11-07)
src\mac_top.v (22919, 2017-11-11)
src\mac_tx.v (13101, 2017-11-07)
src\miim\eth_clockgen.v (5603, 2005-12-13)
src\miim\eth_outputcontrol.v (6412, 2005-12-13)
src\miim\eth_shiftreg.v (6843, 2005-12-13)
src\miim\timescale.v (3153, 2005-12-13)
src\phy_int.v (8513, 2017-11-07)
src\reg_int.v (10230, 2017-11-07)
src\rmon\RMON_addr_gen.v (11354, 2006-06-25)
src\rmon\RMON_ctrl.v (10097, 2006-06-25)
src\rmon\RMON_dpram.v (1292, 2006-01-19)
src\rmon.v (9224, 2017-11-07)
src\rx\broadcast_filter.v (5144, 2017-11-07)
src\rx\crc_chk.v (6212, 2017-11-07)
src\rx\mac_rx_add_chk.v (6743, 2017-11-07)
src\rx\mac_rx_ctrl.v (23102, 2018-07-21)
src\rx\mac_rx_FF.v (26032, 2017-11-07)
src\tx\CRC_gen.v (7274, 2006-01-19)
src\tx\flow_ctrl.v (7767, 2006-01-19)
src\tx\MAC_tx_addr_add.v (5860, 2006-01-19)
src\tx\MAC_tx_Ctrl.v (22985, 2006-06-25)
src\tx\MAC_tx_FF.v (26442, 2006-06-25)
src\tx\Ramdon_gen.v (5537, 2006-01-19)
src\clk (0, 2017-11-11)
src\miim (0, 2017-11-11)
src\rmon (0, 2017-11-11)
src\rx (0, 2017-11-11)
src\tx (0, 2017-11-11)
src (0, 2017-11-11)
近期下载者：
相关文件：
收藏者：