S32K144_MDK5_Can
所属分类：单片机开发
开发工具：C/C++
文件大小：8310KB
下载次数：34
上传日期：2018-08-09 15:55:09
上 传 者：
WalkerXiao
说明： S32K144 GPIO的操作，Uart，TIM，CAN的配置
(S32K144 GPIO operation, Uart, TIM, CAN configuration)
文件列表:
S32K144_MDK5_Can (0, 2018-07-19)
S32K144_MDK5_Can\drvADC.c (8229, 2018-02-05)
S32K144_MDK5_Can\drvADC.h (6395, 2018-02-05)
S32K144_MDK5_Can\drvCAN.c (17241, 2018-02-26)
S32K144_MDK5_Can\drvCAN.h (4393, 2018-02-09)
S32K144_MDK5_Can\drvFTM.c (18751, 2018-03-21)
S32K144_MDK5_Can\drvFTM.h (1420, 2018-02-06)
S32K144_MDK5_Can\drvGPIO.c (9946, 2018-03-01)
S32K144_MDK5_Can\drvGPIO.h (3114, 2018-02-05)
S32K144_MDK5_Can\drvPIT.c (4110, 2018-02-09)
S32K144_MDK5_Can\drvPIT.h (314, 2018-02-04)
S32K144_MDK5_Can\drvSCI.c (6093, 2018-03-01)
S32K144_MDK5_Can\drvSCI.h (583, 2018-03-01)
S32K144_MDK5_Can\EventRecorderStub.scvd (339, 2018-02-10)
S32K144_MDK5_Can\ISR.c (2497, 2018-02-09)
S32K144_MDK5_Can\JLinkLog.txt (58948, 2018-03-21)
S32K144_MDK5_Can\JLinkSettings.ini (758, 2018-02-10)
S32K144_MDK5_Can\Listings (0, 2018-04-16)
S32K144_MDK5_Can\Listings\led.map (63672, 2018-02-03)
S32K144_MDK5_Can\Listings\S32K144.map (81110, 2018-03-22)
S32K144_MDK5_Can\Listings\startup_s32k144.lst (130988, 2018-03-21)
S32K144_MDK5_Can\main.c (2864, 2018-03-22)
S32K144_MDK5_Can\Objects (0, 2018-04-16)
S32K144_MDK5_Can\Objects\clock_manager.crf (496852, 2018-02-03)
S32K144_MDK5_Can\Objects\clock_manager.d (1684, 2018-02-03)
S32K144_MDK5_Can\Objects\clock_manager.o (542256, 2018-02-03)
S32K144_MDK5_Can\Objects\clock_s32k144.crf (496545, 2017-07-26)
S32K144_MDK5_Can\Objects\clock_s32k144.d (2188, 2017-07-26)
S32K144_MDK5_Can\Objects\clock_s32k144.o (562928, 2017-07-26)
S32K144_MDK5_Can\Objects\clock_s32k1xx.crf (539399, 2018-02-03)
S32K144_MDK5_Can\Objects\clock_s32k1xx.d (2190, 2018-02-03)
S32K144_MDK5_Can\Objects\clock_s32k1xx.o (655892, 2018-02-03)
S32K144_MDK5_Can\Objects\croutine.crf (47298, 2017-08-01)
S32K144_MDK5_Can\Objects\croutine.d (1471, 2017-08-01)
S32K144_MDK5_Can\Objects\croutine.o (43588, 2017-08-01)
S32K144_MDK5_Can\Objects\drvadc.crf (449144, 2018-03-21)
S32K144_MDK5_Can\Objects\drvadc.d (601, 2018-03-21)
S32K144_MDK5_Can\Objects\drvadc.o (496896, 2018-03-21)
S32K144_MDK5_Can\Objects\drvcan.crf (458770, 2018-03-21)
S32K144_MDK5_Can\Objects\drvcan.d (632, 2018-03-21)
... ...
/**
** @ingroup soc_header
** @defgroup soc_header_usage Header File Usage
** @{
**
** ## Introduction ##
**
** The following lines describe our recommendations of usage for the S32 SDK
** header files that are supposed to improve both code reuse and code
** portability.\n
** It presents typical use cases such as:
** - 1. Initialize register
** - 2. Initialize bit / bit-field
** - 3. Set bit-field in register
** - 4. Clear bit-field in register
** - 5. Read bit / bit-field
** - 6. Initialize bit using read/modify/write solution
** - 7. Modifying register values when at least 1 bit is w1c
** - 8. Using Interrupts
** .
** Any assignment of a hard coded value is highly discouraged. It is recommended
** the usage of variables or macros for code consistency and reuse reasons.\n
** Information contained in the Header Files:
** - Interrupt vector numbers\n
** Example:
** @code
** HardFault_IRQn = -13
** MemoryManagement_IRQn = -12
** BusFault_IRQn = -11
** ...
** @endcode
**
** - Peripheral device memory map\n
** Example:
** @code
** typedef struct {
** ...
** __IO uint32_t YOFS;
** __IO uint32_t G;
** __IO uint32_t UG;
** __IO uint32_t CLPS;
** ...
** } ADC_Type, *ADC_MemMapPtr;
** @endcode
**
** - Peripheral device register access macros:\n
** + a macro which speecifies the bit-field mask
** + a macro which speecifies the bit-field offset
** + a macro which speecifies the bit-field width
** + a macro which maps a value to a bit-field
** .
** Example:
** @code
** #define ADC_YOFS_YOFS_MASK 0xFFu
** #define ADC_YOFS_YOFS_SHIFT 0u
** #define ADC_YOFS_YOFS_WIDTH 8u
** #define ADC_YOFS_YOFS(x) (((uint32_t)(((uint32_t)(x))< General form:
** @code
** _BASE_PTRS->regName = value;
** @endcode
**
** Example:
** @code
** #define PIN_PTR 5U
** PORTC->PCR[PIN_PTR] = regValue;
** @endcode
**
** ### 2. Initialize bit / bit-field \n###
**
** This method is used for initializing a bit or bit-field.\n
** The benefit of using this method is that modifications of register addresses
** or bit-field offsets will not require code changes when this method is used.
** \n
** General form:
** @code
** _BASE_PTRS->regName &= ~MASK;
** _BASE_PTRS->regName |= (value << SHIFT) & MASK;
** @endcode
**
** Example:
** @code
** #define PIN_IDX 5U
** GPIO_PORT->PTOR &= ~GPIO_PTOR_PTTO_MASK;
** GPIO_PORT->PTOR |= GPIO_PTOR_PTTO(PIN_IDX);
** @endcode
**
** ### 3. Set bit-field in register \n###
**
** This method is used to perform a bitwise OR between a bit-field and a given
** value.\n
**
** General form:
** @code
** _BASE_PTRS->regName |= (value << shift) & MASK ;
** @endcode
**
** Example:
** @code
** GPIO_PORT->PTOR |= (value << GPIO_PTOR_PTTO_SHIFT) & GPIO_PTOR_PTTO_MASK;
** @endcode
**
** ### 4. Clear bit-field in register \n###
**
** This method is used for clearing a bit-field in a register.\n
** For registers where there is at least one w1c bit please see section 8.\n
**
** General form:
** @code
** _BASE_PTRS->regName &= ~MASK;
** @endcode
**
** Example:
** @code
** GPIO_PORT->PTOR &= ~GPIO_PTOR_PTTO_MASK;
** @endcode
**
** ### 5. Read bit / bit-field \n###
**
** This method is used for reading the value of a bit-field from a register.
**
** General form:
** @code
** x = (_BASE_PTRS->regName & mask) >> shift
** @endcode
**
** Example:
** @code
** pcr_mux_value = (base->PCR[pin] & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT;
** @endcode
**
** ### 6. Initialize bit using read/modify/write solution ###
**
** This method is used for clearing / setting a value to a bit in a
** register taking into consideration the previous value.\n
** For w1c bits please consult section 8.
**
** General form:
** @code
** regValue = _BASE_PTRS->regName;
** regValue &= ~MASK;
** regValue |= (value << shift) & MASK;
** _BASE_PTRS->regName = regValue;
** @endcode
**
** Example:
** @code
** regValue = base->PCR[pin];
** regValue &= ~(PORT_PCR_MUX_MASK);
** regValue |= PORT_PCR_MUX(pcr_mux_value);
** base->PCR[pin] = regValue;
** @endcode
**
** ### 7. Modifying register values when at least 1 bit is w1c \n###
** When a register has at least one W1C bit different approaches are suggested
** depending on each particular case:
** - clearing a w1c bit in registers where there are only w1c bits\n
** For this case it is recommended that the bit mask is written at the
** register address.\n
** General form:
** @code
** _BASE_PTRS->regName = MASK;
** @endcode
**
** Example:
** @code
** LPI2C_BASE_PTRS->MSR = LPI2C_MSR_RDF_MASK;
** @endcode
**
** - clearing a w1c bit in registers where there are also "normal" bits\n
** For this case it is recommended that a read-modify-write method is
** used with the mask of the bit-field that will leave the values of
** the other bits unchanged.\n
** General form:
** @code
** _BASE_PTRS->regName |= MASK;
** @endcode
**
** Example:
** @code
** CMP_BASE_PTRS->C0 |= CMP_C0_CFF_MASK;
** @endcode
**
** - clearing a "normal" bit-field in registers where there are also w1c
** bits \n
** For this case it is recommended that a special mask is applied to
** the register. The mask should be created by applying an AND
** operation between the negated mask of the bit-field that is
** intended to be cleared and the negated masks of all the w1c
** bit-fields.\n
** General form:
** @code
** MASK = ~BITFIELD_MASK & ~W1C_BITFIELDS_MASKS
** _BASE_PTRS->regName &= MASK;
** @endcode
**
** Example:
** @code
** MASK = ~CMP_C0_SE_MASK & (~CMP_C0_CFR_MASK & ~CMP_C0_CFF_MASK);
** CMP_BASE_PTRS->C0 &= MASK;
** @endcode
**
** - setting a "normal" bit-field in registers where there are also w1c
** bits \n
** For this case it is recommended that a clearing is done as in the
** previous step and then the bit-field is set as in step 3\n
** General form:
** @code
** MASK = ~BITFIELD_MASK & ~W1C_BITFIELDS_MASKS
** _BASE_PTRS->regName &= MASK;
** _BASE_PTRS->regName |= (value << shift) & MASK;
** @endcode
**
** Example:
** @code
** MASK = ~CMP_C0_SE_MASK & (~CMP_C0_CFR_MASK & ~CMP_C0_CFF_MASK);
** CMP_BASE_PTRS->C0 &= MASK;
** CMP_BASE_PTRS->C0 |= (value< Example: \n
** Enable WakeUp interrupt for instance = 0
** @code
** uint32_t instance = 0;
**
** const IRQn_Type g_flexcanWakeUpIrqId[] = CAN_Wake_Up_IRQS;
**
** INT_SYS_EnableIRQ(g_flexcanWakeUpIrqId[instance]);
** @endcode
**
** @}
*/
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