文件列表:

Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\automake.log (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\bitgen.ut (497, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.bgn (5168, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.bit (212467, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.drc (38, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.cmd_log (1189, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\_impact.log (3551, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\_impact.cmd (980, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.lso (6, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.mcs (597440, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\simple_led.ise (5291, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\simple_led.dhp (1500, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.ngm (99675, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.pad_txt (41808, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.pcf (2842, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.prj (28, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.prm (718, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.sig (253, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.stx (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.syr (13818, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.ucf (2151, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.ucf.untf (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.ut (497, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg.v (7716, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\seven_seg_cclktemp.bit (212467, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\__projnav.log (25594, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\work\hdllib.ref (63, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\work\vlg6F\seven_seg.bin (15534, 2005-08-29)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\work\vlg6F\seven__seg.bin (15679, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\work\vlg6F (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\work (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\dump.xst\seven_seg.prj\ngx\opt (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\dump.xst\seven_seg.prj\ngx\notopt (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\dump.xst\seven_seg.prj\ngx (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\dump.xst\seven_seg.prj (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst\dump.xst (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\xst (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\_ngo\netlist.lst (82, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\_ngo (0, 2005-11-28)
Lab_ISE_Led\3SLC_SimpleLED_Verilog_ISE63\__projnav\bitgen.rsp (497, 2005-11-28)
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Memec Design Spartan-3 LC Development Board Simple LED VHDL Reference Design Target: Xilinx XC3S400-4PQ208C Contents: seven_seg.vhd VHDL source code seven_seg.ucf User Constraint File s2e3lc_led.bit FPGA bitfile for JTAG configuration s2e3lc_led.mcs PROM file Description: This design takes the on-board 50 MHz, de-skews it, and divides it down to 20 MHz using a DLL. This 20 MHz clock is then divided down by 8M to create an enable signal. The clock and enable feed a counter that counts 0 to 9 on the seven segment display. Bits 1-4 of the dip switch control LED1 - LED4. On reset, the binary value of the dip switch gets loaded into the seven segment counter. Push button switch PUSH1 controls a state machine: push/release once to freeze the counter; push/release again to start it up again. For technical assistance, contact your local Memec Design distributor office (Memec, Insight or Impact) or send an e-mail to: rdc@ins.memec.com www.memec.com/xilinxkits

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