vhdl4
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：47KB
下载次数：5
上传日期：2011-05-17 11:11:41
上 传 者：
zyx030166
说明： verilog实验：输入输出都是4为2进制数的8位数字选择器
(verilog experiment: inputs and outputs are 4 to 2 8-bit hexadecimal number selector)
文件列表:
vhdl4\lab4.cr.mti (457, 2011-05-15)
vhdl4\lab4.mpf (55128, 2011-05-15)
vhdl4\lianxi4.bmp (2359350, 2011-05-14)
vhdl4\slec8.v (485, 2011-05-14)
vhdl4\slec_test.v (707, 2011-05-14)
vhdl4\vsim.wlf (40960, 2011-05-15)
vhdl4\work\@_opt\vopt2jeeti (749, 2011-05-14)
vhdl4\work\@_opt\vopt634bti (1927, 2011-05-14)
vhdl4\work\@_opt\vopt64ad9h (68, 2011-05-14)
vhdl4\work\@_opt\vopt9js8ti (701, 2011-05-14)
vhdl4\work\@_opt\vopt9kza9h (1726, 2011-05-14)
vhdl4\work\@_opt\voptdwe478 (316, 2011-05-14)
vhdl4\work\@_opt\voptg391ah (973, 2011-05-14)
vhdl4\work\@_opt\voptkjyy9h (452, 2011-05-14)
vhdl4\work\@_opt\voptkvjvq9 (3020, 2011-05-14)
vhdl4\work\@_opt\voptq3kt9h (4264, 2011-05-14)
vhdl4\work\@_opt\voptqb9rq9 (7040, 2011-05-14)
vhdl4\work\@_opt\voptv35qsi (23536, 2011-05-14)
vhdl4\work\@_opt\voptvw9mcv (734, 2011-05-14)
vhdl4\work\@_opt\_deps (1095, 2011-05-14)
vhdl4\work\@_opt1\vopt22amdx (1927, 2011-05-15)
vhdl4\work\@_opt1\vopt5izidx (701, 2011-05-15)
vhdl4\work\@_opt1\vopt92mfdx (316, 2011-05-15)
vhdl4\work\@_opt1\voptghy5ex (3020, 2011-05-15)
vhdl4\work\@_opt1\voptjhj2yi (7040, 2011-05-15)
vhdl4\work\@_opt1\voptq8vzgq (854, 2011-05-15)
vhdl4\work\@_opt1\voptyhkrdx (749, 2011-05-15)
vhdl4\work\@_opt1\_deps (627, 2011-05-15)
vhdl4\work\mux_8\_primary.dat (701, 2011-05-15)
vhdl4\work\mux_8\_primary.dbs (1927, 2011-05-15)
vhdl4\work\mux_8\_primary.vhd (749, 2011-05-15)
vhdl4\work\test\_primary.dat (973, 2011-05-15)
vhdl4\work\test\_primary.dbs (1726, 2011-05-15)
vhdl4\work\test\_primary.vhd (68, 2011-05-15)
vhdl4\work\_info (773, 2011-05-15)
vhdl4\work\_vmake (26, 2011-05-15)
vhdl4\work\@_opt (0, 2011-05-14)
vhdl4\work\@_opt1 (0, 2011-05-15)
vhdl4\work\mux_8 (0, 2011-05-15)
vhdl4\work\test (0, 2011-05-15)
... ...
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