文件列表:

RTL exercises (0, 2018-08-25)
RTL exercises\combi_logic.vhd (440, 2018-08-25)
RTL exercises\counter.vhd (1709, 2018-08-25)
RTL exercises\counter_up_down.vhd (1057, 2018-08-25)
RTL exercises\ram.vhd (1032, 2018-08-25)
RTL exercises\sequence_det.vhd (2343, 2018-08-25)
RTL exercises\tb_combi_logic.vhd (1077, 2018-08-25)
RTL exercises\tb_counter.vhd (2800, 2018-08-25)
RTL exercises\tb_counter_up_down.vhd (3114, 2018-08-25)
RTL exercises\tb_ram.vhd (1882, 2018-08-25)
RTL exercises\tb_sequence_dec.vhd (2792, 2018-08-25)

# VHDL Programming Training for FPGA ## by [Tertiary Infotech Pte. Ltd](https://www.tertiarycourses.com.sg/) These are the exercise files used for [VHDL Programming Training for FPGA](https://www.tertiarycourses.com.sg/vhdl-programming-fpga-training.html) course. The course outline can be found in https://www.tertiarycourses.com.sg/vhdl-programming-fpga-training.html https://www.tertiarycourses.com.my/vhdl-programming-fpga-training.html

Day 1

FPGA Design FLOW
Motivation

Module 1 : Introduction to VHDL

• Library & Packages
• Entity/Modes
• Architecture

Module 2: VHDL Data Types

• Language Elements
• Identifiers
• Literals
• Types
• Conversion (Advance)
• Object Types
• TEXTIO

Module 3: Operators

• Logical Operator
• Relational Operators
• Arithmetic Operator
• Resize function
• Shift Operators
• Multiplying Operators
• Miscellaneous Operators

Module 4: Concurrent Statements

• Aggregates
• Drivers
• Concurrent Statement 
• Component Instantiation
• Block Statement
• Generate Statement

Module 5: Sequential Statements

• Process statement / Sensitivity List
• Wait statement
• IF statement
• Case statement
• Loop
• Define Range
• Variables
• Variables Vs Signals

Module 6: Configuration

• Generic
• Operator Overloading
• Attributes

Module 7: Lab Exercise

• Combinational Logic

Day 2

Module 8: State Machine

1. Mealy 
2. Moore

Module 9: Simulation

• Steps of simulation / Simulation Deltas
• Inertia Delay / Transport delay
• Test bench

Module 10: Lab Activities

• Design Entry
• Writing VHDL code 
• Test bench 
• Simulating VHDL code with Vivado (Xilinx)
• Synthesize the code

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