文件列表:

can\bench\verilog\can_testbench.v (87107, 2006-04-25)
can\bench\verilog\can_testbench_defines.v (5386, 2006-04-25)
can\bench\verilog\CVS\Entries (152, 2006-05-17)
can\bench\verilog\CVS\Repository (18, 2006-05-17)
can\bench\verilog\CVS\Root (13, 2006-05-17)
can\bench\verilog\CVS (0, 2006-05-17)
can\bench\verilog\timescale.v (3822, 2003-02-09)
can\bench\verilog (0, 2006-05-17)
can\bench (0, 2006-05-17)
can\rtl\verilog\can_acf.v (18889, 2005-04-08)
can\rtl\verilog\can_bsp.v (63089, 2004-11-23)
can\rtl\verilog\can_btl.v (14081, 2004-10-28)
can\rtl\verilog\can_crc.v (4630, 2004-02-08)
can\rtl\verilog\can_defines.v (5611, 2004-05-12)
can\rtl\verilog\can_fifo.v (19354, 2005-03-10)
can\rtl\verilog\can_ibo.v (4056, 2004-02-08)
can\rtl\verilog\can_register.v (4465, 2004-02-08)
can\rtl\verilog\can_registers.v (37463, 2005-03-18)
can\rtl\verilog\can_register_asyn.v (4642, 2004-02-08)
can\rtl\verilog\can_register_asyn_syn.v (4729, 2004-02-08)
can\rtl\verilog\can_register_syn.v (4578, 2004-02-08)
can\rtl\verilog\can_top.v (24677, 2004-10-25)
can\rtl\verilog\CVS\Entries (647, 2006-05-17)
can\rtl\verilog\CVS\Repository (16, 2006-05-17)
can\rtl\verilog\CVS\Root (13, 2006-05-17)
can\rtl\verilog\CVS (0, 2006-05-17)
can\rtl\verilog (0, 2006-05-17)
can\rtl (0, 2006-05-17)
can (0, 2006-05-17)

////////////////////////////////////////////////////////////////////// //// //// //// README.txt //// //// //// //// //// //// This file is part of the CAN Protocol Controller //// //// http://www.opencores.org/projects/can/ //// //// //// //// //// //// Author(s): //// //// Igor Mohor //// //// igorm@opencores.org //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2002, 2003, 2004 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// //// The CAN protocol is developed by Robert Bosch GmbH and //// //// protected by patents. Anybody who wants to implement this //// //// CAN IP core on silicon has to obtain a CAN protocol license //// //// from Bosch. //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: README.txt,v $ // Revision 1.1 2004/05/12 15:58:41 igorm // Core improved to pass all tests with the Bosch VHDL Reference system. // // // // This CAN Controller was tested with the Bosch VHDL Reference Model and passed all the tests. Because of the licensing issue it can not be published on the Opencores web site. The Can Controller was also implemented in real HW (12 boards were constantly talking to each other). The included test bench is not a real test bench and should be improved. However a volunteer is needed for such a job. I can provide some help but am not willing to write it by myself. Best regards, Igor Mohor

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