文件列表:

HomeworkQuestion (0, 2018-08-28)
HomeworkQuestion\HWSetEQ1.vhd (2296, 2018-08-28)
HomeworkQuestion\HWSetEQ2.vhd (2106, 2018-08-28)
HomeworkQuestion\HWSetEQ3.vhd (2490, 2018-08-28)
HomeworkQuestion\HWsetCQ1.vhd (724, 2018-08-28)
HomeworkQuestion\HWsetCQ2.vhd (1479, 2018-08-28)
HomeworkQuestion\problem3new.vhd (1552, 2018-08-28)
PROJECT3 (0, 2018-08-28)
PROJECT3\GONDHALEKAR_WAJE_PROJECT3.pdf (926503, 2018-08-28)
PROJECT3\Module1_Deliverables (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1 (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1 (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1 (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\LAB1.qpf (1298, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\LAB1.qsf (3792, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\LAB1.qws (2083, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\LAB1.vhd (295, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\c5_pin_model_dump.txt (4757, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db (0, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\.cmp.kpt (202, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.(0).cnf.cdb (894, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.(0).cnf.hdb (741, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.asm.qmsg (2792, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.asm.rdb (804, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cbx.xml (81, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.bpm (735, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.cdb (91009, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.hdb (117009, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.idb (1079, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.logdb (13201, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp.rdb (28928, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cmp_merge.kpt (206, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ff_0c_fast.hsd (1518173, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ff_125c_fast.hsd (1515994, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ff_85c_fast.hsd (1520835, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ff_n40c_fast.hsd (1517071, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ii_125c_slow.hsd (1505735, 2018-08-28)
PROJECT3\Module1_Deliverables\Module1_Deliverables\Lab1\Lab1Part1\Lab1Part1\db\LAB1.cyclonev_io_sim_cache.ii_85c_slow.hsd (1500561, 2018-08-28)
... ...

# Programmable_logic_design This is repository for course ECEN 5863.

Project 1:

Project Members: Vikrant Waje, Anay Gondhalekar

Evaluation of Altera MAX10 FPGA and creating a soft processor core

- Used various IP blocks of MAX10 FPGA such as ADC, JTAG, memory, Avalon bus interface and softcore processor
- Created a NIOS 2 softcore processor from FPGA fabric by using the Qsys software. Assigned memory address so that it could load a simple program and display the output. The UART was used to send the data and text to terminal

Project 2:

Project Members: Vikrant Waje, Chutao Wei

Evaluation of Microsemi Smartfusion FPGA

- Used the On chip Analog Compute engine of A2F200M3F FPGA Evaluation kit to convert the analog values of potentiometer into digital values which were displayed on Putty
- Made a multi-functional system that could switch between various modes such as multimeter mode, web-server mode and LED test mode. The IP address would be displayed in webserver mode, voltage across potentiometer would be displayed on Putty in multimeter mode and LED's would blink in LED test mode
- Timing analysis was done on various modules such as binary counter, 32 bit shift register. Clock domain crossing was taken care of and also false path were removed to improve the performance of the fitter. The timing analysis was done using Microsemi Libero development software

Project 3:

Project Members: Vikrant Waje, Anay Gondhalekar

Evaluation of Altera DE-1 SOC and Xilinx Pynq Z1

-Designed Real time Clock to display time on on seven segment leds of Altera DE1-SOC. The design included modules such as clock divider, counters written in VHDL.
- Developed Morse code generator for DE-1 SOC using Quartus Prime FPGA development environment
- Evaluated the Pynq Z1 board by using the on board switches to blink various LED's on board using python on Jupyter Notebook online IDE

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：