teacher_uart
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1880KB
下载次数：6
上传日期：2018-08-29 23:41:26
上 传 者：
abc1997
说明： 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件
(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
文件列表:
teacher_uart\teacher_uart\project3.cache\wt\gui_handlers.wdf (3884, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\java_command_handlers.wdf (1610, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\project.wpc (122, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\synthesis.wdf (5390, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\synthesis_details.wdf (100, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\webtalk_pa.xml (4565, 2018-06-01)
teacher_uart\teacher_uart\project3.cache\wt\xsim.wdf (256, 2018-06-01)
teacher_uart\teacher_uart\project3.hw\hw_1\hw.xml (835, 2018-06-01)
teacher_uart\teacher_uart\project3.hw\project3.lpr (343, 2018-06-01)
teacher_uart\teacher_uart\project3.hw\webtalk\.xsim_webtallk.info (59, 2018-06-20)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_1.xml (212, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_10.xml (228, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_2.xml (226, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_3.xml (233, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_4.xml (411, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_5.xml (233, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_6.xml (233, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_7.xml (235, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_8.xml (214, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\.jobs\vrs_config_9.xml (214, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.init_design.begin.rst (182, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.init_design.end.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.opt_design.begin.rst (182, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.opt_design.end.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.place_design.begin.rst (182, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.place_design.end.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.route_design.begin.rst (182, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.route_design.end.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.vivado.begin.rst (182, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.vivado.end.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\.Vivado_Implementation.queue.rst (0, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\gen_run.xml (5186, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\htr.txt (401, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\init_design.pb (3730, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\ISEWrap.js (7308, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\ISEWrap.sh (1623, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\opt_design.pb (7442, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\place_design.pb (11723, 2018-06-01)
teacher_uart\teacher_uart\project3.runs\impl_1\project.wdf (3634, 2018-06-01)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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