xapp1064
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:221KB
下载次数:9
上传日期:2018-09-09 22:23:04
上 传 者:
pwst
说明: 用于spartan 6的iserdes2/oserdes2参考设计
(Clock Generator Designs
clock_generator_ddr_s8_diff.v/vhd
clock_generator_pll_s16_diff.v/vhd
clock_generator_pll_s8_diff.v/vhd
clock_generator_sdr_s8_diff.v/vhd)
文件列表:
XAPP1064\Verilog_Source (0, 2011-03-01)
XAPP1064\Verilog_Source\Macros (0, 2011-03-01)
XAPP1064\Verilog_Source\Macros\clock_generator_ddr_s8_diff.v (6394, 2010-02-03)
XAPP1064\Verilog_Source\Macros\clock_generator_pll_s16_diff.v (9051, 2010-02-03)
XAPP1064\Verilog_Source\Macros\clock_generator_pll_s8_diff.v (9646, 2010-02-03)
XAPP1064\Verilog_Source\Macros\clock_generator_sdr_s8_diff.v (6166, 2010-02-19)
XAPP1064\Verilog_Source\Macros\phase_detector.v (10743, 2011-07-18)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_ddr_s8_diff.v (8499, 2012-01-10)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_ddr_s8_se.v (8367, 2009-11-27)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_pll_s16_diff.v (20233, 2010-08-10)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_pll_s8_diff.v (19509, 2010-08-10)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_clk_sdr_s8_diff.v (4941, 2010-02-19)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_ddr_s8_diff.v (10998, 2010-02-05)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_ddr_s8_se.v (13594, 2010-02-17)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s16_diff.v (11620, 2010-05-19)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s8_diff.v (11711, 2010-12-06)
XAPP1064\Verilog_Source\Macros\serdes_1_to_n_data_s8_se.v (13581, 2010-12-01)
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_ddr_s8_diff.v (9045, 2010-02-17)
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_ddr_s8_se.v (8928, 2010-02-17)
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s16_diff.v (10667, 2010-06-22)
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s8_diff.v (9458, 2010-06-09)
XAPP1064\Verilog_Source\Macros\serdes_n_to_1_s8_se.v (8854, 2010-02-17)
XAPP1064\Verilog_Source\Top level examples (0, 2011-03-01)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR (0, 2011-03-01)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\tb_top_nto1_ddr.v (4669, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.ucf (428, 2009-11-16)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_rx.v (5393, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.ucf (364, 2009-11-16)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_diff_tx.v (5219, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.ucf (523, 2009-11-16)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_rx.v (5351, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.ucf (256, 2009-11-16)
XAPP1064\Verilog_Source\Top level examples\BUFIO2 DDR\top_nto1_ddr_se_tx.v (5140, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\PLL (0, 2011-03-01)
XAPP1064\Verilog_Source\Top level examples\PLL\tb_top_nto1_pll.v (4850, 2009-12-08)
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx.ucf (428, 2009-11-16)
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx.v (5283, 2009-11-23)
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.ucf (645, 2009-11-23)
XAPP1064\Verilog_Source\Top level examples\PLL\top_nto1_pll_diff_rx_and_tx.v (6234, 2009-11-23)
... ...
*******************************************************************************
** Copyright 2009–2011 Xilinx, Inc. All rights reserved.
** This file contains confidential and proprietary information of Xilinx, Inc. and
** is protected under U.S. and international copyright and other intellectual property laws.
*******************************************************************************
** ____ ____
** / /\/ /
** /___/ \ / Vendor: Xilinx
** \ \ \/
** \ \ readme.txt Version: 1.1
** / / Date Last Modified: January 6 2011
** /___/ /\ Date Created: November 6 2009
** \ \ / \ Associated Filename: xapp10***.zip
** \___\/\___\
**
** Device: Spartan 6
** Purpose: ISERDES and OSERDES use in Spartan 6
** Reference: XAPP10***.pdf
** Revision History: Revision 1.0 initial release
** Revision 1.1 see individual files for details
** main change is separate level of hierarchy for phase detector logic
**
*******************************************************************************
**
** Disclaimer:
**
** This disclaimer is not a license and does not grant any rights to the materials
** distributed herewith. Except as otherwise provided in a valid license issued to you
** by Xilinx, and to the maximum extent permitted by applicable law:
** (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
** AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
** INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
** FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
** or tort, including negligence, or under any other theory of liability) for any loss or damage
** of any kind or nature related to, arising under or in connection with these materials,
** including for any direct, or any indirect, special, incidental, or consequential loss
** or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
** as a result of any action brought by a third party) even if such damage or loss was
** reasonably foreseeable or Xilinx had been advised of the possibility of the same.
**
** Critical Applications:
**
** Xilinx products are not designed or intended to be fail-safe, or for use in any application
** requiring fail-safe performance, such as life-support or safety devices or systems,
** Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
** or any other applications that could lead to death, personal injury, or severe property or
** environmental damage (individually and collectively, "Critical Applications"). Customer assumes
** the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
** to applicable laws and regulations governing limitations on product liability.
** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
*******************************************************************************
This readme describes how to use the files that come with XAPP10***.
*******************************************************************************
** IMPORTANT NOTES **
1)
2)
*******************************************************************************
Included Files
Macros
Clock Generator Designs
clock_generator_ddr_s8_diff.v/vhd
clock_generator_pll_s16_diff.v/vhd
clock_generator_pll_s8_diff.v/vhd
clock_generator_sdr_s8_diff.v/vhd
Clock Receivers
serdes_1_to_n_clk_ddr_s8_diff.v/vhd
serdes_1_to_n_clk_ddr_s8_se.v/vhd
serdes_1_to_n_clk_pll_s16_diff.v/vhd
serdes_1_to_n_clk_pll_s8_diff.v/vhd
serdes_1_to_n_clk_pll_s8_se.v/vhd
serdes_1_to_n_clk_sdr_s8_diff.v/vhd
Data Receivers
serdes_1_to_n_data_ddr_s8_diff.v/vhd
serdes_1_to_n_data_ddr_s8_se.v/vhd
serdes_1_to_n_data_s16_diff.v/vhd
serdes_1_to_n_data_s8_diff.v/vhd
serdes_1_to_n_data_s8_se.v/vhd
phase_detector.v/vhd
Data Transmitters
serdes_n_to_1_ddr_s8_diff.v/vhd
serdes_n_to_1_ddr_s8_se.v/vhd
serdes_n_to_1_s16_diff.v/vhd
serdes_n_to_1_s8_diff.v/vhd
serdes_n_to_1_s8_se.v/vhd
Top Level Examples ucfs, and testbenches
n to 1 DDR BUFIO2 based transmitter
n to 1 DDR BUFIO2 based receiver
n to 1 PLL based transmitter
n to 1 PLL based receiver
n to 1 PLL based transmitter (high serdes factors)
n to 1 PLL based receiver (high serdes factors)
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