文件列表:

DMAMUX_RequestGen (0, 2018-09-25)
DMAMUX_RequestGen\EWARM (0, 2018-09-25)
DMAMUX_RequestGen\EWARM\Project.ewd (45141, 2018-01-03)
DMAMUX_RequestGen\EWARM\Project.ewp (30212, 2018-01-03)
DMAMUX_RequestGen\EWARM\Project.eww (151, 2018-01-03)
DMAMUX_RequestGen\EWARM\startup_stm32h743xx.s (40194, 2018-01-03)
DMAMUX_RequestGen\EWARM\stm32h743xx_flash.icf (1598, 2018-01-03)
DMAMUX_RequestGen\Inc (0, 2018-09-25)
DMAMUX_RequestGen\Inc\main.h (2964, 2018-01-03)
DMAMUX_RequestGen\Inc\stm32h7xx_hal_conf.h (14976, 2018-01-03)
DMAMUX_RequestGen\Inc\stm32h7xx_it.h (3214, 2018-01-03)
DMAMUX_RequestGen\MDK-ARM (0, 2018-09-25)
DMAMUX_RequestGen\MDK-ARM\Project.uvoptx (16528, 2018-01-03)
DMAMUX_RequestGen\MDK-ARM\Project.uvprojx (20066, 2018-01-03)
DMAMUX_RequestGen\MDK-ARM\startup_stm32h743xx.s (44968, 2018-01-03)
DMAMUX_RequestGen\MDK-ARM\STM32H743ZI_Nucleo (0, 2018-09-25)
DMAMUX_RequestGen\MDK-ARM\STM32H743ZI_Nucleo\Exe (0, 2018-09-25)
DMAMUX_RequestGen\MDK-ARM\STM32H743ZI_Nucleo\Exe\STM32H743ZI-Nucleo.sct (549, 2018-01-03)
DMAMUX_RequestGen\Src (0, 2018-09-25)
DMAMUX_RequestGen\Src\main.c (14820, 2018-01-03)
DMAMUX_RequestGen\Src\stm32h7xx_it.c (5746, 2018-01-03)
DMAMUX_RequestGen\Src\system_stm32h7xx.c (11335, 2018-01-03)
DMAMUX_RequestGen\SW4STM32 (0, 2018-09-25)
DMAMUX_RequestGen\SW4STM32\startup_stm32h743xx.s (36796, 2018-01-03)
DMAMUX_RequestGen\SW4STM32\STM32H743ZI_Nucleo (0, 2018-09-25)
DMAMUX_RequestGen\SW4STM32\STM32H743ZI_Nucleo\.cproject (11805, 2018-01-03)
DMAMUX_RequestGen\SW4STM32\STM32H743ZI_Nucleo\.project (4665, 2018-01-03)
DMAMUX_RequestGen\SW4STM32\STM32H743ZI_Nucleo\STM32H743ZITx_FLASH.ld (5852, 2018-01-03)

/** @page DMAMUX_RequestGen DMA & DMAMUX request generator Example @verbatim ******************** (C) COPYRIGHT 2017 STMicroelectronics ******************* * @file DMA/DMAMUX_RequestGen/readme.txt * @author MCD Application Team * @version V1.2.0 * @date 29-December-2017 * @brief Description of the DMA & request generator Example. ****************************************************************************** * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** @endverbatim @par Example Description This example shows how to use the DMA with the DMAMUX request generator to generate DMA transfer requests upon LPTIM2 output signal, knowing that the LPTIM2 is configured in PWM with 2sec period. The example uses the BDMA channel 0 configured in memory to peripheral mode with the DMAMUX request generator 0. At the beginning of the main program the HAL_Init() function is called to reset all the peripherals, initialize the Flash interface and the systick. The SystemClock_Config() function is used to configure the system clock for STM32H743xx Devices : The CPU at 400MHz The HCLK for D1 Domain AXI and AHB3 peripherals , D2 Domain AHB1/AHB2 peripherals and D3 Domain AHB4 peripherals at 200MHz. The APB clock dividers for D1 Domain APB3 peripherals, D2 Domain APB1 and APB2 peripherals and D3 Domain APB4 peripherals to run at 100MHz. The BDMA channel 0 is configured in memory to peripheral mode to ensure data transfer from the source transmission buffer (SRC_Buffer_LED1_Toggle) to the GPIOB ODR register (in order to toggle LED1). The DMA is configured in circular mode so the transfer will restart automatically each time the amount of data to be transmitted has been reached. @note the Domain 3 BDMA has access to Domain 3 SRAMs and peripherals only, thus the source buffer (SRC_Buffer_LED1_Toggle) has been placed to the D3 SRAM (@0x38000000) The DMAMUX request generator block is configured using function "HAL_DMAEx_ConfigMuxRequestGenerator" with the following parameters : - SignalID : set to HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT which corresponds to LPTIM2 output signal. - Polarity : Set to RISING to use rising edge the LPTIM2 output signal for DMA requests generation. - RequestNumber : 1 i.e. on each rising edge of the LPTIM2 output signal, a DMA request is generated. The DMA request generator is then enabled using function “HAL_DMAEx_EnableMuxRequestGenerator”. The function "LPTIM_Config" is then used to configure the LPTIM2 to generate a PWM with a period of 2sec. Note that the example doesn’t need to configure a GPIO to LPTIM2 output alternate function as the LPTIM2 output signal is used internally to trigger the DMAMUX request generator in order to generate DMA transfer requests every 2sec. Then the DMA transfer is started in non-blocking mode using the HAL function "HAL_DMA_Start_IT" On each LPTIM2 output event (i.e every 2sec) the DMAMUX request generator generates a DMA request. As consequence the DMA will serve the request and write a new value to the GPIOB ODR register to toggle the LED1 without any CPU intervention. As consequence LED1 will toggle every 2sec. The CPU is only used to intercept a DMA transfer interrupt error and DMAMUX overflow interrupt if any and sets the LED3 (Red LED) to On in this case. STM32 board's LEDs can be used to monitor the transfer status: - LED1 toggles every 2 seconds. - LED3 is ON when there is an error during the DMA transfer. @note Care must be taken when using HAL_Delay(), this function provides accurate delay (in milliseconds) based on variable incremented in SysTick ISR. This implies that if HAL_Delay() is called from a peripheral ISR process, then the SysTick interrupt must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. To change the SysTick interrupt priority you have to use HAL_NVIC_SetPriority() function. @note The application needs to ensure that the SysTick time base is always set to 1 millisecond to have correct HAL operation. @Note If the application is using the DTCM/ITCM memories (@0x20000000/ 0x0000000: not cacheable and only accessible by the Cortex M7 and the MDMA), no need for cache maintenance when the Cortex M7 and the MDMA access these RAMs. If the application needs to use DMA(or other masters) based access or requires more RAM, then the user has to: - Use a non TCM SRAM. (example : D1 AXI-SRAM @ 0x24000000) - Add a cache maintenance mechanism to ensure the cache coherence between CPU and other masters(DMAs,DMA2D,LTDC,MDMA). - The addresses and the size of cacheable buffers (shared between CPU and other masters) must be properlydefined to be aligned to L1-CACHE line size (32 bytes). @Note It is recommended to enable the cache and maintain its coherence, but depending on the use case It is also possible to configure the MPU as "Write through", to guarantee the write access coherence. In that case, the MPU must be configured as Cacheable/Bufferable/Not Shareable. Even though the user must manage the cache coherence for read accesses. Please refer to the AN4838 “Managing memory protection unit (MPU) in STM32 MCUs” Please refer to the AN4839 “Level 1 cache on STM32F7 Series” @par Directory contents - DMA/DMAMUX_RequestGen/Inc/stm32h7xx_hal_conf.h HAL configuration file - DMA/DMAMUX_RequestGen/Inc/stm32h7xx_it.h DMA interrupt handlers header file - DMA/DMAMUX_RequestGen/Inc/main.h Header for main.c module - DMA/DMAMUX_RequestGen/Src/stm32h7xx_it.c DMA interrupt handlers - DMA/DMAMUX_RequestGen/Src/main.c Main program - DMA/DMAMUX_RequestGen/Src/system_stm32h7xx.c STM32H7xx system source file @par Hardware and Software environment - This example runs on STM32H743xx device. - This example has been tested with STM32H743ZI-NUCLEO board and can be easily tailored to any other supported device and development board. @par How to use it ? In order to make the program work, you must do the following : - Open your preferred toolchain - Rebuild all files and load your image into target memory - Run the example *

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