aud_expand
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：63KB
下载次数：3
上传日期：2018-10-12 14:29:02
上 传 者：
网发开合联临
说明： 就是用FPGA写的音频加嵌模块。代码很多慢慢看
(it is Using FPGA to write audio module.)
文件列表:
aud_expand.v (16591, 2015-11-19)
AudClkFifo.v (8865, 2015-01-20)
AudioOut.v (7859, 2016-10-13)
AudioPkt.v (28938, 2016-10-13)
edh_anc_rx.v (11825, 2015-11-19)
edh_autodetect.v (20984, 2015-11-19)
edh_crc.v (14112, 2015-11-19)
edh_crc16.v (4237, 2015-11-19)
edh_errcnt.v (5625, 2015-11-19)
edh_flags.v (11081, 2015-11-19)
edh_fly_field.v (5824, 2015-11-19)
edh_fly_fsm.v (20039, 2015-11-19)
edh_fly_horz.v (11433, 2015-11-19)
edh_fly_vert.v (14128, 2015-11-19)
edh_flywheel.v (24738, 2015-11-19)
edh_loc.v (7915, 2015-11-19)
ACPcreate.v (6586, 2015-05-08)
ADPcreate.v (10147, 2015-01-20)
afd_insert.v (19177, 2015-08-14)
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