BPSK
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：10521KB
下载次数：12
上传日期：2018-10-18 20:39:18
上 传 者：
5744428
说明： BPSK的完整程序,testbench已经写啦,可以模拟仿真的完成程序
(BPSK's complete program, testbench has been written, you can simulate the completion process.)
文件列表:
BPSK\bpf.mif (198, 2016-09-12)
BPSK\bpfCOEFF_auto0_0.mif (36, 2016-09-12)
BPSK\bpfCOEFF_auto0_1.mif (36, 2016-09-12)
BPSK\bpfCOEFF_auto0_2.mif (36, 2016-09-12)
BPSK\bpfCOEFF_auto0_3.mif (36, 2016-09-12)
BPSK\bpfCOEFF_auto0_4.mif (36, 2016-09-12)
BPSK\bpfCOEFF_auto0_5.mif (36, 2016-09-12)
BPSK\bpffilt_decode_rom.mif (51, 2016-09-12)
BPSK\BPSK.gise (17950, 2018-09-19)
BPSK\BPSK.xise (38060, 2018-09-19)
BPSK\demod_PSK.bld (3485, 2016-09-14)
BPSK\demod_PSK.cmd_log (3996, 2016-09-14)
BPSK\demod_PSK.lso (6, 2016-09-14)
BPSK\demod_PSK.ncd (472366, 2016-09-14)
BPSK\demod_PSK.ngc (22221, 2016-09-14)
BPSK\demod_PSK.ngd (1435307, 2016-09-14)
BPSK\demod_PSK.ngr (27455, 2016-09-14)
BPSK\demod_PSK.pad (25431, 2016-09-14)
BPSK\demod_PSK.par (5210, 2016-09-14)
BPSK\demod_PSK.pcf (221, 2016-09-14)
BPSK\demod_PSK.prj (191, 2016-09-14)
BPSK\demod_PSK.ptwx (17226, 2016-09-14)
BPSK\demod_PSK.stx (0, 2016-09-14)
BPSK\demod_PSK.syr (23443, 2016-09-14)
BPSK\demod_PSK.twr (3479, 2016-09-14)
BPSK\demod_PSK.twx (21334, 2016-09-14)
BPSK\demod_PSK.unroutes (159, 2016-09-14)
BPSK\demod_PSK.v (1759, 2016-09-14)
BPSK\demod_PSK.xpi (46, 2016-09-14)
BPSK\demod_PSK.xst (1250, 2016-09-14)
BPSK\demod_PSK_envsettings.html (18256, 2018-09-19)
BPSK\demod_PSK_guide.ncd (472366, 2016-09-14)
BPSK\demod_PSK_map.map (5897, 2016-09-14)
BPSK\demod_PSK_map.mrp (48523, 2016-09-14)
BPSK\demod_PSK_map.ncd (269406, 2016-09-14)
BPSK\demod_PSK_map.ngm (2650438, 2016-09-14)
BPSK\demod_PSK_map.xrpt (29344, 2016-09-14)
BPSK\demod_PSK_ngdbuild.xrpt (13228, 2016-09-14)
BPSK\demod_PSK_pad.csv (25464, 2016-09-14)
BPSK\demod_PSK_pad.txt (128232, 2016-09-14)
... ...
The following files were generated for 'bpf' in directory
D:\ISE\new\BPSK\ipcore_dir\
Opens the IP Customization GUI:
Allows the user to customize or recustomize the IP instance.
* bpf.mif
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* bpf.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* bpf.ngc
* bpf.v
* bpf.veo
* bpfCOEFF_auto0_0.mif
* bpfCOEFF_auto0_1.mif
* bpfCOEFF_auto0_2.mif
* bpfCOEFF_auto0_3.mif
* bpfCOEFF_auto0_4.mif
* bpfCOEFF_auto0_5.mif
* bpffilt_decode_rom.mif
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* bpf.veo
IP Symbol Generator:
Generate an IP symbol based on the current project options'.
* bpf.asy
* bpf.mif
SYM file generator:
Generate a SYM file for compatibility with legacy flows
* bpf.sym
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* bpf_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* _xmsgs/pn_parser.xmsgs
* bpf.gise
* bpf.xise
Deliver Readme:
Readme file for the IP.
* bpf_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* bpf_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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