UVM寄存器模型
所属分类：其他
开发工具：Verilog
文件大小：81KB
下载次数：20
上传日期：2018-10-21 13:09:59
上 传 者：
donnyli
说明： uvm寄存器模型的示例和具体用法，包括仿真平台的使用
(Examples and specific usage of UVM register model, including the use of simulation platform.)
文件列表:
UVM寄存器模型 (0, 2018-10-21)
UVM寄存器模型\register_model (0, 2018-10-21)
UVM寄存器模型\register_model\apb (0, 2018-10-21)
UVM寄存器模型\register_model\apb\.imc.trace (0, 2015-05-28)
UVM寄存器模型\register_model\apb\demo.sh (2325, 2015-05-28)
UVM寄存器模型\register_model\apb\sv (0, 2018-10-21)
UVM寄存器模型\register_model\apb\sv\apb_checker.sv (9517, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_collector.sv (5837, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_config.sv (5769, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_env.sv (5985, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_if.sv (3920, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_agent.sv (3611, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_driver.sv (25, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_driver_new.sv (6167, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_driver_orig.sv (6019, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_if.sv (3393, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_seq_lib.sv (7540, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_master_sequencer.sv (2099, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_monitor.sv (6463, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_pkg.sv (1675, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_slave_agent.sv (3878, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_slave_driver.sv (3552, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_slave_if.sv (2791, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_slave_seq_lib.sv (3987, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_slave_sequencer.sv (2150, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_transfer.sv (2090, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\apb_types.sv (1199, 2015-05-28)
UVM寄存器模型\register_model\apb\sv\reg_to_apb_adapter.sv (2642, 2015-05-28)
UVM寄存器模型\register_model\apb\tb (0, 2018-10-21)
UVM寄存器模型\register_model\apb\tb\apb_demo_scoreboard.sv (4415, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\demo_config.sv (2224, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\demo_tb.sv (2435, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\demo_top.sv (1684, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\dut_dummy.v (105, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\seq_test.sv (842, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\sim_command.tcl (2206, 2015-05-28)
UVM寄存器模型\register_model\apb\tb\test_lib.sv (5157, 2015-05-28)
UVM寄存器模型\register_model\clock_and_reset (0, 2018-10-21)
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lab11_regmodel
This lab is an introduction to register modeling using UVM1.1.
You MUST source the setup.csh file first before running this lab.
This lab uses Cadence's iregGen tool to convert an IP-XACT XML register
specification into a UVM register model.
iregGen requires Perl and looks for a Perl installation directory in $PATH.
iregGen also requires the Perl XML libraries.
if you get the following error, it means your Perl installation may not have
the XML libraries.
iregGen Error: ‘can’t locate XML/LibXML.pm’.
You might find that you need to download the Perl XML libraries from CPAN.org,
as some Perl installations don't have the XML libs as standard.
If that's the case, you can leave PATH as it is, and simply point PERL5LIB env
var to the place that you downloaded and unpacked the XML libraries.
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