nesfpga
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:1217KB
下载次数:0
上传日期:2018-10-28 01:56:07
上 传 者:
sh-1993
说明: 任天堂娱乐系统的一种简单FPGA实现
(A Simple FPGA Implementation of the Nintendo Entertainment System)
文件列表:
.project (1051, 2018-10-28)
APU (0, 2018-10-28)
APU\APU_Main.v (25723, 2018-10-28)
APU\ac97wav.py (610, 2018-10-28)
APU\apu.py (9834, 2018-10-28)
APU\apu_convert.py (388, 2018-10-28)
APU\apu_tb.py (1559, 2018-10-28)
APU\clk_util.py (157, 2018-10-28)
APU\cpu_bus.py (857, 2018-10-28)
APU\nsf.py (2495, 2018-10-28)
APU\smb.nsf (17084, 2018-10-28)
CartridgeROM.vhd (2010, 2018-10-28)
CartridgeROM_Coregen.vhd (1995, 2018-10-28)
ColorPalette.vhd (2101, 2018-10-28)
Coregen (0, 2018-10-28)
Coregen\chr_rom_NEStress.ngc (48727, 2018-10-28)
Coregen\chr_rom_smb.ngc (57250, 2018-10-28)
Coregen\coregen.cgc (126764, 2018-10-28)
Coregen\coregen.cgp (530, 2018-10-28)
Coregen\prg_rom_NESStress.ngc (118786, 2018-10-28)
Coregen\prg_rom_smb.ngc (161338, 2018-10-28)
Genesys_NES.vhd (6681, 2018-10-28)
HDMI (0, 2018-10-28)
HDMI\HDMIController.vhd (5425, 2018-10-28)
HDMI\iic_init.v (15495, 2018-10-28)
HDMI\tft_interface.v (24245, 2018-10-28)
NES_2A03 (0, 2018-10-28)
NES_2A03\ClockDivider.vhd (3246, 2018-10-28)
NES_2A03\DanPack.vhd (1925, 2018-10-28)
NES_2A03\Dan_2A03.vhd (8422, 2018-10-28)
NES_2A03\SRAM.vhd (1667, 2018-10-28)
NES_2A03\T65.vhd (16750, 2018-10-28)
NES_2A03\T65_ALU.vhd (8200, 2018-10-28)
NES_2A03\T65_MCode.vhd (26023, 2018-10-28)
NES_2A03\T65_Pack.vhd (4921, 2018-10-28)
NES_Mainboard.vhd (4759, 2018-10-28)
NES_Pack.vhd (4040, 2018-10-28)
PPU (0, 2018-10-28)
PPU\Loopy_Scrolling.vhd (3315, 2018-10-28)
... ...
NESFPGA
=======
This project implements a simplified version of the
Nintendo Entertainment System on an FPGA, that can execute Super Mario Bros.
Getting Started
---------------
I used the Digilent Genesys FPGA board, which is currently the only board this
project works on.
Sadly, you will need a version of Xilinx ISE software to synthesize this project.
I used version 14.5, the free Webpack Edition should be fine.
Create a new project, and first include the top module Genesys_NES.vhd,
to see what other files are missing. Don't forget the constraints file nes_top.ucf.
Then add every .vhd and .v file, except the TestBenches, and CartridgeROM*.vhd
### Cartridge
CartridgeROM.vhd reads the ROM data from .dat files in the directory roms/.
The default filenames are 'roms/smb_chr.dat' and 'roms/smb_prg.dat'.
These files are already shipped with the project, but you can generate them
with tools/romconv.py. Beware, this project only supports 32 KiB ROMs.
XST should support the ROM inferrence style in CartridgeROM.vhd, but this is rather slow.
For faster synthesis, use CartridgeROM_Coregen.vhd and include
the appropriate .ngc files from the Coregen directory.
This directory also includes the Coregen project files, and romconv.py can be
modified to generate the necessary .coe files from .nes ROMs.
### MyHDL Part
Since the APU is programmed in MyHDL, it needs to be converted to VHDL or Verilog
code for synthesis. apu_convert.py does this for you, but you will need to install
MyHDL (at least version 0.7).
Alternatively, for synthesis you can just use the pregenerated file APU/APU_Main.v.
Directory Overview
------------------
NES_2A03 - The modified CPU from Dan Leach's NES-On-a-FPGA project
PPU - Implementation of the NES 2C02
APU - MyHDL code and testbench for the APU
TestBenches - Various VHDL based testbenches
tools - Tools for generating ROM helper files, and framebuffer viewer
roms - ROM files in .nes and converted form
HDMI - Chrontel CH7301C interface from xps_tft
ac97 - The 3rd party AC97 module with my wrapper
synaesthesia - First attempt at a ISE-independent build system... Ignore for now
Flashing the FPGA board
-----------------------
To persistently save the bistream on the FPGA boards flash RAM, you
need to use Xilinx iMPact. These are the settings i used to generate
the MCS file:
- Parallel BPI Single Boot
- Virtex 5 / 32M
- 16 bit width
- 28F256P30 (not 512, the genesys schematic is lying)
Testbenches
-----------
### NES_Framebuffer_TB.vhd
This is the testbench for simulating everything down from NES_Mainboard.
But beware, you will need a fast and expensive simulator for this to be useful.
It writes the framebuffer data to fbdump_top.out.
The FBView tool in tools/fbview can be used to view this file.
It includes a build script, but you will need a working gcc and the SDL
library to compile it.
The testbench also includes a primitive way for simulating controller pad inputs
in the process CONTROLLER_INPUT. It uses 1 for not pressed and 0 for pressed.
From left to right, the button mapping is "Right, Left, Down, Up, Start, Select, B, A"
### apu_tb.py
Unlike the other testbenches, this is found in the APU directory.
To use it, you will need Py65. Use these commands to get
and configure python to find it:
$ cd APU
$ git clone https://github.com/mnaberez/py65
$ export PYTHONPATH=py65
To start simulating the first song of the SMB nsf, use this command:
$ python apu_tb.py smb.nsf 0
It will write the file smb-0.wav to the output directory.
I recommend you to acquire a recent version of PyPy, and use it instead
of standard CPython, as it speeds up the simulation by orders of magnitude
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