sdram_control_burst
所属分类：VHDL/FPGA/Verilog
开发工具：MultiPlatform
文件大小：150KB
下载次数：329
上传日期：2006-03-14 23:47:52
上 传 者：
silentecho
说明： 精简的sdram读写控制器例子，适用于数据采集系统，verilog，只支持burst方式的读写
(streamlined read and write SDRAM controller example, applied to the data acquisition system, Verilog. only supports burst mode read and write)
文件列表:
test (0, 2006-01-18)
test\ise (0, 2006-01-18)
test\ise\test.npl (544, 2006-01-20)
test\ise\__projnav (0, 2006-01-18)
test\ise\__projnav\coregen.rsp (110, 2006-01-25)
test\ise\__projnav\runXst_tcl.rsp (32, 2006-01-20)
test\ise\__projnav\test_flowplus.gfl (2808, 2006-01-20)
test\ise\__projnav\test.gfl (3942, 2006-01-20)
test\ise\__projnav\fpga.xst (955, 2006-01-20)
test\ise\fpga.ngr (99869, 2006-01-20)
test\ise\fpga.ngc (63532, 2006-01-20)
test\ise\test.dhp (1135, 2006-01-25)
test\ise\coregen.log (665, 2006-01-25)
test\ise\coregen.prj (7472, 2006-01-18)
test\ise\__projnav.log (188231, 2006-01-20)
test\ise\automake.log (0, 2006-01-20)
test\ise\fpga.prj (28, 2006-01-20)
test\ise\fpga.cmd_log (1539, 2006-01-20)
test\ise\fpga.syr (18041, 2006-01-20)
test\ise\xst (0, 2006-01-18)
test\ise\xst\work (0, 2006-01-18)
test\ise\xst\work\vlg22 (0, 2006-01-18)
test\ise\xst\work\vlg22\fpga.bin (26969, 2006-01-20)
test\ise\xst\work\hdllib.ref (43, 2006-01-20)
test\ise\fpga.stx (0, 2006-01-20)
test\ise\fpga_vhdl.prj (0, 2006-01-20)
test\ise\fpga.lso (6, 2006-01-20)
test\modelsim (0, 2006-01-18)
test\modelsim\work (0, 2006-01-18)
test\modelsim\work\_info (734, 2006-01-20)
test\modelsim\work\fpga (0, 2006-01-18)
test\modelsim\work\fpga\_primary.vhd (1114, 2006-01-20)
test\modelsim\work\fpga\verilog.asm (38933, 2006-01-20)
test\modelsim\work\fpga\_primary.dat (5579, 2006-01-20)
test\modelsim\work\@v51 (0, 2006-01-18)
test\modelsim\work\@v51\_primary.vhd (421, 2006-01-19)
test\modelsim\work\@v51\verilog.asm (6535, 2006-01-19)
test\modelsim\work\@v51\_primary.dat (656, 2006-01-19)
test\modelsim\work\top (0, 2006-01-18)
test\modelsim\work\top\_primary.vhd (66, 2006-01-19)
... ...
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