FPGAfinish1
所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:7KB
下载次数:5
上传日期:2018-11-20 20:29:41
上 传 者:
asdzzk
说明: BASYS2板子用的VHDL语言实现简易数字钟,有调整和闹钟功能
(The BASYS2 board uses VHDL language to realize simple digital clock. It has functions of adjustment and alarm clock.)
文件列表:
finish1\cyw3_0.bit (72759, 2014-04-13)
finish1\cyw3_0.ucf (613, 2014-04-14)
finish1\cyw3_0.unroutes (154, 2014-04-13)
finish1\cyw_0.v (5034, 2014-04-14)
finish1 (0, 2014-04-14)
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