OFDM_802_11
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：280KB
下载次数：24
上传日期：2018-11-24 15:01:57
上 传 者：
阴天小象YYY
说明： ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。
(Source code of transmission link and reception link of OFDM)
文件列表:
OFDM_802_11\OFDM_RX_802_11\IPCORE\Ch_CmxMul.v (129164, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\Ch_CmxMul.xco (1816, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\Complex_Multiplier.v (123000, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\Complex_Multiplier.xco (1826, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FFT_ipcore.v (1746010, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FFT_ipcore.xco (2161, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FreComp_PhaseRot.v (683196, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FreComp_PhaseRot.xco (1850, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FreComp_PhaseTrans.v (154662, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\FreComp_PhaseTrans.xco (1862, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\mult.v (29322, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\IPCORE\mult.xco (1840, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_ChEstEqu_tb.m (2735, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_ChEstEqu_wr_dat_in.m (4834, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_PhaseTrack_tb.m (3554, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_PhaseTrack_wr_dat_in.m (4812, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_RX_tb.m (12585, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_RX_wr_dat_in.m (4445, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\OFDM_SYN_tb.m (6004, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\pilots_802_11.m (1098, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\preamble_802_11.m (917, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MATLAB\SIM_thresold_Q.m (9592, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Acc_Sum.v (1093, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Appr_Mag.v (1115, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\ChEstEqu_lpre.txt (104, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Ch_buf.v (1907, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Ch_EstEqu.v (5482, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Ch_EstEqu_tb.v (2674, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Coarse_Time_Synch.v (3125, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Comp_Acc_Sum.v (1414, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\DataSymDem.v (1701, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Delay2n.v (1100, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Delay_reg.v (740, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\FFT.v (3511, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Fine_Time_Synch.v (3782, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\FreComp.v (3908, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\FreComp_PhaseRotAcc.v (2105, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\Freoff_Est_Comp.v (2952, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\iCFO_Appr_Mag.v (1120, 2017-12-15)
OFDM_802_11\OFDM_RX_802_11\MY_SOURCES\iCFO_est.v (12028, 2017-12-15)
... ...
# IEEE 802.11 OFDM-based transceiver system
This repos contains the implementation of IEEE 802.11 (i.e. Wifi) OFDM-based transceiver system. This is stored in 2 separate parts, i.e. transmitter (TX) and receiver (RX).
Each part includes implementation files stored in **MY_SOURCES** and **IPCORE**, and simulation golden model stored in **MATLAB**.
**MY_SOURCES** contains hdl files using verilog to implement the sub-modules (*.v) of systems and to make a testbench files (*_tb.v). There are some pre-computed cofficient sets defined by the standard (e.g. preamble) are stored in '*.txt' files. OFDM_TX_802_11.v and OFDM_RX_802_11.v are the top modules of transmitter and receiver systems, respectively.
**IPCORE** contains the configured files of IPCores instantiated by impelemented systems. The IPCores are generated using ISE Design Tool.
**MATLAB** contains matlab files that simulate 802.11 OFDM signals as a golden model for implementation. The matlab files are also used to generate test vector for testbench and verify the output files from testbench.
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