zhuangtaiji
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：51KB
下载次数：0
上传日期：2018-12-02 17:03:17
上 传 者：
刘一二12
说明： 使用modelsim软件设计和仿真
1.画状态图,采用三段式实现对8 位序列数“11010011”的检测
(Design and simulation using Modelsim software
1. Drawing the state diagram and using three-segment method to realize the detection of 8-bit sequence number "11010011")
文件列表:
zhuangtaiji\vsim.wlf (417792, 2018-11-28)
zhuangtaiji\work\ztj\verilog.asm (17240, 2018-11-28)
zhuangtaiji\work\ztj\verilog.rw (563, 2018-11-28)
zhuangtaiji\work\ztj\_primary.dat (1624, 2018-11-28)
zhuangtaiji\work\ztj\_primary.dbs (1321, 2018-11-28)
zhuangtaiji\work\ztj\_primary.vhd (1787, 2018-11-28)
zhuangtaiji\work\ztj_tp\verilog.asm (6848, 2018-11-28)
zhuangtaiji\work\ztj_tp\verilog.rw (547, 2018-11-28)
zhuangtaiji\work\ztj_tp\_primary.dat (631, 2018-11-28)
zhuangtaiji\work\ztj_tp\_primary.dbs (926, 2018-11-28)
zhuangtaiji\work\ztj_tp\_primary.vhd (72, 2018-11-28)
zhuangtaiji\work\_info (647, 2018-11-28)
zhuangtaiji\work\_vmake (26, 2018-11-28)
zhuangtaiji\zhuangtaiji.cr.mti (391, 2018-11-28)
zhuangtaiji\zhuangtaiji.mpf (79070, 2018-11-28)
zhuangtaiji\ztj.v (1272, 2018-11-28)
zhuangtaiji\ztj.v.bak (2, 2018-11-28)
zhuangtaiji\ztj_tp.v (460, 2018-11-28)
zhuangtaiji\ztj_tp.v.bak (2, 2018-11-28)
zhuangtaiji\work\ztj (0, 2018-12-02)
zhuangtaiji\work\ztj_tp (0, 2018-12-02)
zhuangtaiji\work (0, 2018-12-02)
zhuangtaiji (0, 2018-12-02)
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