zhouzeming_hls_hls_sobel_1_0
所属分类：VHDL/FPGA/Verilog
开发工具：C/C++
文件大小：78KB
下载次数：7
上传日期：2018-12-06 16:25:33
上 传 者：
Lnier
说明： VIVADO HLS写的sobel检测，封装成IP核。
(The sobel detection written by VIVADO HLS is encapsulated into an IP core.)
文件列表:
component.xml (66680, 2018-12-06)
constraints\hls_sobel.xdc (90, 2018-12-06)
constraints\hls_sobel_ooc.xdc (393, 2018-12-06)
hdl\verilog\arithm_pro.v (15269, 2018-12-06)
hdl\verilog\AXIvideo2Mat.v (37628, 2018-12-06)
hdl\verilog\CvtColor.v (19122, 2018-12-06)
hdl\verilog\CvtColor_1.v (12912, 2018-12-06)
hdl\verilog\Dilate.v (83991, 2018-12-06)
hdl\verilog\Erode.v (83718, 2018-12-06)
hdl\verilog\fifo_w8_d1_A.v (3094, 2018-12-06)
hdl\verilog\Filter2D.v (44523, 2018-12-06)
hdl\verilog\Filter2D_k_buf_0_eOg.v (1672, 2018-12-06)
hdl\verilog\hls_sobel.v (31929, 2018-12-06)
hdl\verilog\hls_sobel_ap_rst_n_if.v (519, 2018-12-06)
hdl\verilog\hls_sobel_CONTROL_BUS_if.v (9105, 2018-12-06)
hdl\verilog\hls_sobel_mac_mulcud.v (1372, 2018-12-06)
hdl\verilog\hls_sobel_mac_muldEe.v (1372, 2018-12-06)
hdl\verilog\hls_sobel_mul_mulbkb.v (782, 2018-12-06)
hdl\verilog\hls_sobel_mux_32_hbi.v (1170, 2018-12-06)
hdl\verilog\hls_sobel_top.v (5983, 2018-12-06)
hdl\verilog\Mat2AXIvideo.v (39910, 2018-12-06)
hdl\verilog\Scale.v (9587, 2018-12-06)
hdl\verilog\Sobel.v (6209, 2018-12-06)
hdl\verilog\SubS.v (18324, 2018-12-06)
drivers\hls_sobel_top_v1_0\data\hls_sobel_top.mdd (559, 2018-12-06)
drivers\hls_sobel_top_v1_0\data\hls_sobel_top.tcl (850, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\Makefile (786, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\xhls_sobel.c (6419, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\xhls_sobel.h (3512, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\xhls_sobel_hw.h (1737, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\xhls_sobel_linux.c (4761, 2018-12-06)
drivers\hls_sobel_top_v1_0\src\xhls_sobel_sinit.c (1162, 2018-12-06)
doc\ReleaseNotes.txt (416, 2018-12-06)
misc\logo.png (4077, 2017-12-16)
bd\bd.tcl (1621, 2018-12-06)
xgui\hls_sobel_v1_0.tcl (1027, 2018-12-06)
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