Verilog代码综合
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:2KB
下载次数:3
上传日期:2018-12-07 22:04:30
上 传 者:
forget12345
说明: 包含乘法器,触发器,状态机,booth乘法器,都用Verilog实现
(Including multipliers, triggers, state machines, booth multipliers, all implemented in Verilog)
文件列表:
mul.v (289, 2018-10-21)
mul_64_tb.v (338, 2018-10-21)
jk_ff_tb.v (277, 2018-10-21)
jk_ff.v (217, 2018-10-21)
mul_4.v (759, 2018-10-31)
mul_4_tb.v (343, 2018-10-31)
string10010_tb.v (332, 2018-11-03)
string10010.v (1169, 2018-11-03)
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