qsysampling
所属分类：其他
开发工具：Verilog
文件大小：24369KB
下载次数：0
上传日期：2018-12-20 09:10:54
上 传 者：
唧唧爱baby
说明： max10在qsy平台采样，在fpga内部通过总线传输
(Max10 is sampled on QSY platform and transmitted through bus in FPGA)
文件列表:
qsysampling\.qsys_edit\caiyang.xml (83830, 2018-12-11)
qsysampling\.qsys_edit\caiyang_schematic.nlv (2999, 2018-12-07)
qsysampling\.qsys_edit\filters.xml (66, 2018-12-06)
qsysampling\.qsys_edit\preferences.xml (486, 2018-12-11)
qsysampling\caiyang\caiyang.bsf (3574, 2018-12-11)
qsysampling\caiyang\caiyang.cmp (461, 2018-12-11)
qsysampling\caiyang\caiyang.html (75163, 2018-12-11)
qsysampling\caiyang\caiyang.xml (250561, 2018-12-11)
qsysampling\caiyang\caiyang_bb.v (298, 2018-12-11)
qsysampling\caiyang\caiyang_generation.rpt (7527, 2018-12-11)
qsysampling\caiyang\caiyang_generation_previous.rpt (7527, 2018-12-07)
qsysampling\caiyang\caiyang_inst.v (626, 2018-12-11)
qsysampling\caiyang\caiyang_inst.vhd (1107, 2018-12-11)
qsysampling\caiyang\synthesis\caiyang.debuginfo (355770, 2018-12-11)
qsysampling\caiyang\synthesis\caiyang.qip (172760, 2018-12-11)
qsysampling\caiyang\synthesis\caiyang.v (24251, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_avalon_st_splitter.sv (17109, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_merlin_master_translator.sv (22645, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_merlin_slave_translator.sv (17338, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_control.sdc (7905, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_control.v (6753, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_control_avrg_fifo.v (7713, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_control_fsm.v (34944, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_sample_store.v (7197, 2018-12-06)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_sample_store_ram.v (4629, 2018-12-06)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_sequencer.v (14835, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_sequencer_csr.v (4312, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_modular_adc_sequencer_ctrl.v (11113, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_reset_controller.sdc (1648, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_reset_controller.v (12329, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_reset_synchronizer.v (3553, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_trace_adc_monitor_core.sv (23670, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_trace_adc_monitor_wa.sv (4864, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_trace_adc_monitor_wa_inst.v (2373, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\altera_trace_monitor_endpoint_wrapper.sv (4354, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\caiyang_altpll_0.v (11473, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\caiyang_avalon_st_adapter.v (13090, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\caiyang_avalon_st_adapter_channel_adapter_0.sv (3657, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\caiyang_avalon_st_adapter_data_format_adapter_0.sv (3526, 2018-12-11)
qsysampling\caiyang\synthesis\submodules\caiyang_avalon_st_adapter_timing_adapter_0.sv (4600, 2018-12-11)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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