FPGA_AutoControl_Xiyiji_by_Jalen_Cheng
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：6632KB
下载次数：1
上传日期：2018-12-24 20:56:56
上 传 者：
Jalen Cheng
说明： 可编程数字系统设计的基本流程
设计输入（原理图文件、硬件描述语言文件、网表输入文件、混合输入文件）项目处理（设计文件检查和编译、设计文件分析和综合、器件适配、设置设计约束）设计校验（生成功能网表、功能仿真、适配后的仿真文件、门级时序仿真）器件编程（生成器件编程文件、器件编程）
原理设计输入方式是利用软件提供的各种原理图库，采用画图的方式进行设计输入。这是一种最为简单和直观的输入方式。原理图输入方式的效率比较低，一般只用于小规模系统设计，或用于在顶层拼接各个已设计完成的电路子模块。
(Basic Flow of Programmable Digital System Design
Design Input (schematic diagram file, hardware description language file, netlist input file, mixed input file) project processing (checking and compiling design documents, analysis and synthesis of design documents, device adaptation, setting design constraints) design verification (generating functional netlist, function simulation, adapted simulation files, gate-level timing simulation) device programming (generating component programming text) Programming of Components and Devices
Principle design input mode is to use various schematic library provided by the software to design input by drawing. This is the simplest and most intuitive way to input. The input mode of schematic diagram is inefficient. It is usually only used for small-scale system design or for splicing each completed circuit sub-module at the top level.)
文件列表:
FPGA系统设计全自动洗衣机设计.pdf (6148585, 2018-12-24)
XIYIJI (0, 2018-03-20)
XIYIJI\XIYIJI (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\.Xil (0, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_ngo (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\_ngo\netlist.lst (291, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\bitgen.xmsgs (22327, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\cg.xmsgs (1743, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\map.xmsgs (24008, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\ngdbuild.xmsgs (367, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\par.xmsgs (1568, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\pn_parser.xmsgs (967, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\trce.xmsgs (1149, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\_xmsgs\xst.xmsgs (47170, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\coregen.cgp (235, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\coregen.log (3058, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.asy (267, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.gise (1400, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.mif (1536, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.ncf (0, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.ngc (6677, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.sym (848, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.vhd (4520, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.vho (4026, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.xco (2205, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4.xise (4978, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4 (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\doc (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\doc\dist_mem_gen_ds322.pdf (42607, 2013-10-14)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\doc\dist_mem_gen_v6_4_vinfo.html (7358, 2013-10-14)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\example_design (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\example_design\dist_mem_gen_v6_4_exdes.ucf (2596, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\example_design\dist_mem_gen_v6_4_exdes.vhd (5295, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\example_design\dist_mem_gen_v6_4_exdes.xdc (2599, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\implement (0, 2018-03-20)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\implement\implement.bat (3386, 2018-01-03)
XIYIJI\XIYIJI\XIYIJI\dist_mem_gen_v6_4\implement\implement.sh (3280, 2018-01-03)
... ...
Core name: Xilinx LogiCORE Distributed Memory Generator
Version: ***
Release: 13.4
Release Date: January 18, 2012
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core,
please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator v6.3
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/DIST_MEM_GEN.htm
2. NEW FEATURES
- ISE 13.4 software support
- Artix-7 Lower Power and Automotive Artix-7 device support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
- Virtex-7
- Virtex-7 -2L
- Virtex-7 -2G
- Virtex-7 XT
- Kintex-7
- Kintex-7 -2L
- Artix-7
- AArtix-7
- Artix-7L
- Zynq-7000*
- Virtex-6 XC CXT/LXT/SXT/HXT
- Virtex-6 XQ LXT/SXT
- Virtex-6 -1L XC LXT/SXT
- Virtex-6 -1L XQ LXT/SXT
- Spartan-6 XC LX/LXT
- Spartan-6 XA LX/LXT
- Spartan-6 XQ LX/LXT
- Spartan-6 -1L XC LX
- Spartan-6 -1L XQ LX
- Virtex-5 XC LX/LXT/SXT/TXT/FXT
- Virtex-5 XQ LX/LXT/SXT/FXT
- Virtex-4 XC LX/SX/FX
- Virtex-4 XQ LX/SX/FX
- Virtex-4 XQR LX/SX/FX
- Spartan-3 XC
- Spartan-3 XA
- Spartan-3A XC 3A / 3A DSP / 3AN
- Spartan-3A XA 3A / 3A DSP
- Spartan-3E XC
- Spartan-3E XA
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
4. RESOLVED ISSUES
The following issues are resolved in v6.3:
- The Distributed Memory Generator IP GUI is not showing the Simple Dual
Port Memory option for the use.
Version Fixed: v6.3
- CR 620314
5. KNOWN ISSUES
There are not known issues for v6.3 of this core at time of release:
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
01/18/2012 Xilinx, Inc. 6.3 ISE 13.4 support; Artix-7L and Automotive Artix-7 device support
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7* and Zynq-7000* device support
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support
04/19/2010 Xilinx, Inc. 5.1 ISE 12.1 support
12/02/2009 Xilinx, Inc. 4.3 ISE 11.4 support; Spartan-6 Lower Power and Automotive Spartan-6 device support
09/16/2009 Xilinx, Inc. 4.2 11.3 support; Virtex-6 Lower Power and Virtex-6 HXT device support
06/24/2009 Xilinx, Inc. 4.1.1 11.2 support; Virtex-6 CXT device support
04/24/2009 Xilinx, Inc. 4.1 11.1 support; Revised to v4.1; Virtex-6 and Spartan-6 support
03/24/2008 Xilinx, Inc. 3.4 10.1 support; Revised to v3.4.
04/02/2007 Xilinx, Inc. 3.3 9.1i support; Revised to v3.3; Spartan-3AN and Spartan-3A DSP support
09/21/2006 Xilinx, Inc. 3.2 8.2i support; Revised to v3.2; Spartan-3A support
07/13/2006 Xilinx, Inc. 3.1 8.2i support; Revised to v3.1
01/18/2006 Xilinx, Inc. 2.1 8.1i support; Revised to v2.1
04/28/2005 Xilinx, Inc. 1.1 7.1i Service Pack 1 support; First release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
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safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
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injury, or severe property or environmental damage
(individually and collectively, "Critical
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