文件列表:

ddr3_sun\ddr3.gise (30108, 2018-12-31)
ddr3_sun\ddr3.xise (47331, 2018-12-31)
ddr3_sun\ddr3_model_isim_beh.exe (94720, 2018-12-31)
ddr3_sun\ddr3_tb.fdo (5454, 2018-12-25)
ddr3_sun\ddr3_tb.udo (380, 2018-08-29)
ddr3_sun\ddr3_tb.v (32493, 2018-09-01)
ddr3_sun\ddr3_tb1.fdo (5459, 2018-12-30)
ddr3_sun\ddr3_tb1.udo (381, 2018-08-31)
ddr3_sun\ddr3_tb1.v (35010, 2018-12-31)
ddr3_sun\ddr3_tb1_beh.prj (4649, 2018-12-31)
ddr3_sun\ddr3_tb1_isim_beh.exe (94720, 2018-12-31)
ddr3_sun\ddr3_tb1_isim_beh.wdb (7041713, 2018-12-31)
ddr3_sun\ddr3_tb1_wave.fdo (426, 2018-08-31)
ddr3_sun\ddr3_tb3.v (948, 2018-09-01)
ddr3_sun\ddr3_tb_wave.fdo (425, 2018-08-29)
ddr3_sun\example_top.fdo (6889, 2018-08-30)
ddr3_sun\example_top.udo (384, 2018-08-30)
ddr3_sun\example_top1.wlf (507904, 2018-08-31)
ddr3_sun\example_top_wave.fdo (429, 2018-08-30)
ddr3_sun\fuse.log (28543, 2018-12-31)
ddr3_sun\fuse.xmsgs (5563, 2018-12-31)
ddr3_sun\fuseRelaunch.cmd (238, 2018-12-31)
ddr3_sun\ipcore_dir\coregen.cgp (239, 2018-08-29)
ddr3_sun\ipcore_dir\coregen.log (258, 2018-08-30)
ddr3_sun\ipcore_dir\create_a.tcl (1254, 2018-08-30)
ddr3_sun\ipcore_dir\create_DDR3.tcl (1257, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\datasheet.txt (2705, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\DDR3.csv (5561, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\docs\ug586_7Series_MIS.pdf (79723, 2013-10-14)
ddr3_sun\ipcore_dir\DDR3\example_design\log.txt (4872, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\create_ise.bat (3137, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_icon_cg.xco (1413, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_basic_cg.xco (3898, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_rdpath_cg.xco (3900, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_ila_wrpath_cg.xco (3899, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_vio_async_in_sync_out_cg.xco (1619, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\ddr_vio_sync_async_out72_cg.xco (1616, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\example_top.cpj (757534, 2018-08-29)
ddr3_sun\ipcore_dir\DDR3\example_design\par\example_top.ucf (29839, 2018-08-29)
... ...

The design files are located at D:/Myprojects/ddr3/ipcore_dir: - DDR3.veo: veo template file containing code that can be used as a model for instantiating a CORE Generator module in a HDL design. - DDR3.xco: CORE Generator input file containing the parameters used to regenerate a core. - DDR3_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. - DDR3_readme.txt: Text file indicating the files generated and how they are used. - DDR3_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project. - DDR3.csv: Includes the pin out information which is used as support file for PlanAhead. - DDR3.gise and DDR3.xise: ISE Project Navigator support files. These are generated files and should not be edited directly. - DDR3 directory. In the DDR3 directory, three folders are created: - docs: This folder contains MIG user guide. - example_design: This folder includes script files to implement and simulate the design. This includes the traffic generator RTL modules and example_top module. - user_design: This folder includes the all RTL modules of controller, phy and user interface RTL modules. UCF file is provided. The example_design and user_design folders contain several other folders and files. All these output folders are discussed in more detail in MIG user guide (ug586_7Series_MIS.pdf) located in docs folder.

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