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zNBfilter.exe (1344040, 2002-05-11)

;************************************************************************************* ;*********************** SECTION 1: FILTER LIBRARY *********************************** ;************************************************************************************* Thank you for trying C2000 Software Collateral. Filter Library is installed in C:\TIDCS\C24\DSP_TBOX\FILTER directory. Digital filters are a common requirement for digital signal processing systems. There are two types of digital filters: Finite impulse response (FIR) and infinite impulse response (IIR) filters. Both the filter modules are available in the filter library. FIR filters require delay line to buffer the past inputs, that is implemented using two methods viz., Linear buffer and Circular buffer. Linear buffer delay line is implemented using DMOV instruction and it requires the delay buffer to be placed in the internal DARAM blocks (B0, B1 & B2 blocks). Circular buffer delay line is implemented using bit reversed addressing technique and it requires appropriate buffer alignment. We have a provided FIR filter modules for both the implementation in generic and fixed order form. Generic FIR Filter modules are implemented in looped code and the fixed order implementation unrolls the loop. Hence the generic FIR filter execution time is more then the fixed order FIR filters. We have made available an ezFIR filter design package (MATLAB script) to interactively generate filter coefficients for the required frequency response characteristics. IIR filter uses the cascade configuration of direct form II structured Second order section (SOS) that reduces sensitivity to coefficient quantization. The SOS’s are commonly referred to as Biquads. The SOS coefficients generated by the MATLAB for given set of filter specification provides unity gain in the pass-band and attenuates the remaining frequency component. Though the input to output gain does not peak above unity, the intermediate node gain in the biquad sections would vary significantly depending on the filter characteristics. Hence, we have made a available a ezIIR filter design package (MATLAB script) that generates scaled second order coefficients without overflow issues in the intermediate nodes. The following table summarizes the set of modules that are available in this library. FILTER LIBRARY |===============|======================================================================| | Module Name | Description | |===============|======================================================================| | FIRFILT_GEN | Generic FIR filter using linear buffer (Looped code) | |---------------|----------------------------------------------------------------------| | FIRFILT_ORD10 | 10th order FIR filter using linear buffer | |---------------|----------------------------------------------------------------------| | FIRFILT_ORD20 | 20th order FIR filter using linear buffer | |---------------|----------------------------------------------------------------------| | FIRFILT_CGEN | Generic FIR filter using circular buffer (Looped code) | |---------------|----------------------------------------------------------------------| | FIRFILT_CORD10| 10th order FIR filter using circular buffer | |---------------|----------------------------------------------------------------------| | FIRFILT_CORD20| 20th order FIR filter using circular buffer | |---------------|----------------------------------------------------------------------| | IIRBIQ16 | Cascade IIR filter (16-bit delay buffer) | |---------------|----------------------------------------------------------------------| | IIRBIQ32 | Cascade IIR filter (32-bit delay buffer) | |======================================================================================| DOCUMENTATION: |===============|======================================================================| | DOC | DIRECTORY LOCATION | |===============|======================================================================| | MODULE DOC | C:\TIDCS\C24\DSP_TBOX\FILTER\DOC\FILTER_MDL.PDF | |---------------|----------------------------------------------------------------------| | STB DOC | C:\TIDCS\C24\DSP_TBOX\FILTER\DOC\FILTER_STB.PDF | |---------------|----------------------------------------------------------------------| | ezFIR DOC | C:\TIDCS\C24\DSP_TBOX\FILTER\DOC\EZFIR.PDF | |---------------|----------------------------------------------------------------------| | ezIIR DOC | C:\TIDCS\C24\DSP_TBOX\FILTER\DOC\EZIIR.PDF | |======================================================================================| ;************************************************************************************* ;******************** SECTION 2: Software Test Bench (STB) *************************** ;************************************************************************************* To facilitate evaluation and deployment of these modules, they are made available as Software Test Benches (STBs) which run as code composer projects on readily available EVMs or eZdsp hardware platforms. Each STB focuses on a particular software module and shows the customer how to invoke it, pass variable or data to it, and how to link it into their systems. Where possible, the module under evaluation is made to interact with other modules such as signal generators, which can provide input stimulus and data-logging modules or PWM-DAC drivers to examine a module's response in a real-time environment. This helps customers to get a more realistic feel of the software module's capability and applicability. Shown below is the STB for IIR filter module. CH0 |--------------| |------------| |-----------| ---->| | | | | | CH0 | | | | | | ---->| | input | | Output | EVMDAC | CH0 | ADC04U_DRV |-----|---->| IIR |-------------->| PWMDAC | ---->| | | | FILTER | | DATALOG | CH0 | | | | | |--->| | --|->| | | | | | | | |--------------| | |------------| | |-----------| | | |-----------------------------| The idea behind the STB strategy to demonstrate the filter module is indeed simple. Analog input signal is sampled at 20Kz through ADC and the sampled digital representation of analog signal is fed to the Filter module. Input to the filter and the filtered output are logged, sent through EVMDAC and PWMDAC so that the user can quickly start evaluating the filter module by varying the input frequency and observing the response.

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