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ft602_uvc_spartan6_fifo32_20171115 (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\ft602_uvc.xise (40709, 2017-02-24)
ft602_uvc_spartan6_fifo32_20171115\ft602_uvc_top_envsettings.html (17592, 2017-10-30)
ft602_uvc_spartan6_fifo32_20171115\ft602_uvc_top_guide.ncd (3413352, 2017-10-27)
ft602_uvc_spartan6_fifo32_20171115\Image (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\Image\ft602_uvc_top.bit (464380, 2017-10-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\.lso (14, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\coregen.cgp (238, 2017-02-24)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\coregen.log (2878, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.asy (634, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.gise (1261, 2017-10-30)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.ncf (0, 2017-10-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.ngc (92778, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.sym (1832, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.v (121188, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.veo (4800, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.xco (1757, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider.xise (4893, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider_flist.txt (223, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\divider_xmdf.tcl (2658, 2017-02-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36 (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.asy (705, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.gise (1276, 2017-10-30)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.ncf (0, 2017-10-27)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.ngc (80141, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.v (5893, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.veo (4350, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.xco (3297, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36.xise (4486, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\doc (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\doc\blk_mem_gen_v7_3_vinfo.html (8311, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\doc\pg058-blk-mem-gen.pdf (7207569, 2013-10-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\example_design (0, 2017-12-06)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\example_design\dpsram_4kx36_exdes.ucf (2777, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\example_design\dpsram_4kx36_exdes.vhd (5179, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\example_design\dpsram_4kx36_exdes.xdc (2720, 2017-02-14)
ft602_uvc_spartan6_fifo32_20171115\ipcore_dir\dpsram_4kx36\example_design\dpsram_4kx36_prod.vhd (10570, 2017-02-14)
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The following files were generated for 'divider' in directory C:\Users\ngocduong.do\Documents\FTDI\FT602\design\ft602_uvc_spar6\ipcore_dir\ XCO file generator: Generate an XCO file for compatibility with legacy flows. * divider.xco Creates an implementation netlist: Creates an implementation netlist for the IP. * divider.ngc * divider.v * divider.veo Creates an HDL instantiation template: Creates an HDL instantiation template for the IP. * divider.veo IP Symbol Generator: Generate an IP symbol based on the current project options'. * divider.asy SYM file generator: Generate a SYM file for compatibility with legacy flows * divider.sym Generate ISE metadata: Create a metadata file for use when including this core in ISE designs * divider_xmdf.tcl Generate ISE subproject: Create an ISE subproject for use when including this core in ISE designs * _xmsgs/pn_parser.xmsgs * divider.gise * divider.xise Deliver Readme: Readme file for the IP. * divider_readme.txt Generate FLIST file: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. * divider_flist.txt Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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