Verilog RTL PreProcessor
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：21564KB
下载次数：0
上传日期：2019-01-21 12:51:24
上 传 者：
Zeus_96
说明： Verilog RTL preprocesor
文件列表:
preprocessverilog (0, 2013-02-10)
preprocessverilog\16FEB2013 (0, 2013-02-10)
preprocessverilog\16FEB2013\bin (0, 2013-02-10)
preprocessverilog\16FEB2013\bin\preprocessverilog (1018, 2013-02-13)
preprocessverilog\16FEB2013\bin\preprocessverilog.bat (869, 2013-02-08)
preprocessverilog\16FEB2013\examples (0, 2012-05-26)
preprocessverilog\16FEB2013\examples\decrypt_data (0, 2012-12-23)
preprocessverilog\16FEB2013\examples\decrypt_data\runme.bat (1463, 2012-12-01)
preprocessverilog\16FEB2013\examples\decrypt_data\runme.csh (1361, 2012-09-28)
preprocessverilog\16FEB2013\examples\decrypt_data\test.v (1057, 2012-09-28)
preprocessverilog\16FEB2013\examples\example_1 (0, 2012-12-23)
preprocessverilog\16FEB2013\examples\example_1\.#runme.csh.1.2 (658, 2012-02-04)
preprocessverilog\16FEB2013\examples\example_1\example_1.v (514, 2012-02-04)
preprocessverilog\16FEB2013\examples\example_1\runme.bat (60, 2012-12-01)
preprocessverilog\16FEB2013\examples\example_1\runme.csh (75, 2012-11-30)
preprocessverilog\16FEB2013\lib (0, 2013-02-10)
preprocessverilog\16FEB2013\lib\designplayer.jar (24011319, 2013-02-13)
preprocessverilog\16FEB2013\LICENSE.txt (1424, 2013-02-09)
preprocessverilog\16FEB2013\setup_env.bat (183, 2013-02-13)
preprocessverilog\16FEB2013\setup_env.csh (800, 2013-02-13)
preprocessverilog\16FEB2013\setup_env.sh (825, 2013-02-13)
**************************************************************************
* *
* Verilog Preprocessor *
* Copyright (C) 2012, edautils.com *
* *
**************************************************************************
Welcome to the free Verilog Preprocessor utlity !!! This utility
is meant for those verilog users who wants to preprocess their verilog
files based upon various compiler directives. This utility has been
implemented in Java and this utility has been packaged as a JAR file.
Goto installation area and source the file 'setup_env.csh' to setup
the environment for this tool. You need to execute this utility as-
preprocessverilog -in foo.v [-out preprocessed_foo.v] [+incdir+dir1+dir2] [+define+macro1+macro2] [-key decryptionKey] [-algorithm AES|RSA|...]
OR
java com.eu.miscedautils.verilogparser.PreProcessVerilog -in foo.v [-out preprocessed_foo.v] [+incdir+dir1+dir2] [+define+macro1+macro2] [-key decryptionKey] [-algorithm AES|RSA|...]
If you do not use the -out switch then the result will be dumped
in a directory name VlogPP inside the rundir. You will fidn the
generated file inside this VlogPP directory with the same file
name.
If you have multiple files you can list down all of them in
a startup file provide that file with -f switch instead of -in.
In this case do not specify the output file name in this case.
All the preprocessed fiiles will be written inside the dir named
'VlogPP' in the run directory.
Examples
========
Have a look onto the examples directory to get a better understanding
of this tool.
FEEDBACK
========
Send feedback to help@edautils.com
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