src

所属分类:VHDL/FPGA/Verilog
开发工具:Verilog
文件大小:7KB
下载次数:14
上传日期:2019-01-22 20:58:54
上 传 者Jelly ma
说明:  假设每个从设备中有可访问APB寄存器16个,位宽均为32比特,16个寄存器的访问地址计算方式为 基址 + 寄存器编号左移2位(byte 偏移)
(Assuming that there are 16 accessible APB registers in each slave device, the bit width is 32 bits, and the access address of 16 registers is calculated by base address + register number left shift 2 bits (byte offset).)

文件列表:
src\apb_bridge.v (5979, 2018-12-07)
src\apb_slave.v (1299, 2018-12-05)
src\apb_slave_tb.v (1275, 2018-12-03)
src\arbiter.v (2944, 2018-11-28)
src\arbiter_tb.v (1009, 2018-11-27)
src\top.v (4476, 2018-12-04)
src\top_tb.v (4429, 2018-12-07)
src\transcript (780, 2018-12-09)
src (0, 2018-12-23)

近期下载者

相关文件


收藏者