clkdivverilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：156KB
下载次数：15
上传日期：2011-05-27 09:08:21
上 传 者：
ky0611
说明： Verilog的时钟分频程序 基于EPM240的入门实验 特权同学
(Verilog program the clock frequency of entry based on experimental privileged students EPM240)
文件列表:
EX1\clkdivverilog\clkdiv.asm.rpt (7470, 2009-07-31)
EX1\clkdivverilog\clkdiv.cdf (326, 2008-11-18)
EX1\clkdivverilog\clkdiv.done (26, 2009-07-31)
EX1\clkdivverilog\clkdiv.dpf (239, 2009-03-23)
EX1\clkdivverilog\clkdiv.fit.rpt (60197, 2009-07-31)
EX1\clkdivverilog\clkdiv.fit.smsg (334, 2009-07-31)
EX1\clkdivverilog\clkdiv.fit.summary (360, 2009-07-31)
EX1\clkdivverilog\clkdiv.flow.rpt (7278, 2009-07-31)
EX1\clkdivverilog\clkdiv.map.rpt (15937, 2009-07-31)
EX1\clkdivverilog\clkdiv.map.summary (300, 2009-07-31)
EX1\clkdivverilog\clkdiv.pin (15371, 2009-07-31)
EX1\clkdivverilog\clkdiv.pof (7855, 2009-07-31)
EX1\clkdivverilog\clkdiv.qpf (909, 2008-10-17)
EX1\clkdivverilog\clkdiv.qsf (2215, 2009-10-29)
EX1\clkdivverilog\clkdiv.qws (530, 2009-10-29)
EX1\clkdivverilog\clkdiv.tan.rpt (59748, 2009-07-31)
EX1\clkdivverilog\clkdiv.tan.summary (971, 2009-07-31)
EX1\clkdivverilog\clkdiv.v (1202, 2009-10-29)
EX1\clkdivverilog\clkdiv.v.bak (1131, 2009-03-23)
EX1\clkdivverilog\clkdiv_assignment_defaults.qdf (40202, 2009-03-17)
EX1\clkdivverilog\sopc_builder_debug_log.txt (0, 2008-10-17)
EX1\clkdivverilog\incremental_db\compiled_partitions\clkdiv.root_partition.map.kpt (10953, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.(0).cnf.cdb (1695, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.(0).cnf.hdb (802, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.asm.qmsg (2190, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.asm_labs.ddb (808, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cbx.xml (88, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.cdb (7547, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.hdb (7499, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.kpt (337, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.logdb (4, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.rdb (14900, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp.tdb (7355, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.cmp0.ddb (25568, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.db_info (137, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.eco.cdb (161, 2009-10-29)
EX1\clkdivverilog\db\clkdiv.fit.qmsg (21482, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.hier_info (946, 2009-07-31)
EX1\clkdivverilog\db\clkdiv.hif (740, 2009-07-31)
... ...
This folder contains data for incremental compilation.
The compiled_partitions sub-folder contains previous compilation results for each partition.
As long as this folder is preserved, incremental compilation results from earlier compiles
can be re-used. To perform a clean compilation from source files for all partitions, both
the db and incremental_db folder should be removed.
The imported_partitions sub-folder contains the last imported QXP for each imported partition.
As long as this folder is preserved, imported partitions will be automatically re-imported
when the db or incremental_db/compiled_partitions folders are removed.
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