文件列表:

m0 (0, 2016-09-20)
m0\AT510-BU-98000-r1p0-00rel0.lst (19504, 2015-10-08)
m0\cortexm0_designstart (0, 2016-09-20)
m0\cortexm0_designstart\cores (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0 (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0ds (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0ds\verilog (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0ds\verilog\CORTEXM0DS.v (6330, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0ds\verilog\cortexm0ds_logic.v (658475, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_dap (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_dap\verilog (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_dap\verilog\CORTEXM0DAP.v (3334, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_integration (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_integration\verilog (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_integration\verilog\CORTEXM0INTEGRATION.v (17890, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_integration\verilog\cortexm0_rst_ctl.v (4031, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\cortexm0_integration\verilog\cortexm0_wic.v (1970, 2015-09-22)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\models (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\models\cells (0, 2016-09-20)
m0\cortexm0_designstart\cores\cortexm0_designstart_r1p0\logical\models\cells\cm0_dbg_reset_sync.v (2871, 2015-09-22)
m0\cortexm0_designstart\Cortex_M0_DesignStart_Design_Kit_Release_Note.pdf (373322, 2015-10-07)
m0\cortexm0_designstart\documentation (0, 2016-09-20)
m0\cortexm0_designstart\documentation\DUI0926A_cortex_m0_designstart_rtl_testbench_r1p0_user_guide.pdf (563301, 2015-10-08)
m0\cortexm0_designstart\implementation_tsmc_ce018fg (0, 2016-09-20)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys (0, 2016-09-20)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\data (0, 2015-10-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\logs (0, 2015-10-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\Makefile (3637, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\reports (0, 2016-09-20)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\reports\dft (0, 2015-10-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\reports\lec (0, 2015-10-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\reports\synthesis (0, 2015-10-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts (0, 2016-09-20)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_clocks.tcl (5632, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_constraints.tcl (19155, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_dft.tcl (18623, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_fm.tcl (10887, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_reports.tcl (4858, 2015-09-22)
m0\cortexm0_designstart\implementation_tsmc_ce018fg\cortex_m0_mcu_system_synopsys\scripts\cmsdk_mcu_system_syn.tcl (21561, 2015-09-22)
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