文件列表:

ALU (0, 2017-07-11)
ALU\ALU.vhd (5097, 2017-07-11)
ALU\operations (0, 2017-07-11)
ALU\operations\AND.vhd (352, 2017-07-11)
ALU\operations\Addition.vhd (832, 2017-07-11)
ALU\operations\Comparison.vhd (306, 2017-07-11)
ALU\operations\Inverter.vhd (342, 2017-07-11)
ALU\operations\Multiply.vhd (989, 2017-07-11)
ALU\operations\OR.vhd (349, 2017-07-11)
ALU\operations\Rand.vhd (458, 2017-07-11)
ALU\operations\Shift.vhd (595, 2017-07-11)
ALU\operations\Subtraction.vhd (1148, 2017-07-11)
ALU\operations\Two'sComplement.vhd (594, 2017-07-11)
ALU\operations\XOR.vhd (796, 2017-07-11)
CU (0, 2017-07-11)
CU\CU.vhd (13873, 2017-07-11)
CU\CU_Plus.vhd (14956, 2017-07-11)
Mux.vhd (531, 2017-07-11)
SAYEH.vhd (8152, 2017-07-11)
TriState.vhd (486, 2017-07-11)
docs (0, 2017-07-11)
docs\datapath.png (122177, 2017-07-11)
docs\instruction_set.png (397746, 2017-07-11)
docs\project definition.pdf (889343, 2017-07-11)
docs\report.docx (357317, 2017-07-11)
docs\report.pdf (1231905, 2017-07-11)
docs\state_machine.png (106864, 2017-07-11)
memory and registers (0, 2017-07-11)
memory and registers\AddressLogic.vhd (1318, 2017-07-11)
memory and registers\AddressUnit.vhd (1218, 2017-07-11)
memory and registers\CacheMemory (0, 2017-07-11)
memory and registers\CacheMemory\CacheController.vhd (4146, 2017-07-11)
memory and registers\CacheMemory\CacheMem.vhd (6171, 2017-07-11)
memory and registers\CacheMemory\CounterUnit.vhd (1114, 2017-07-11)
memory and registers\CacheMemory\DataArray.vhd (846, 2017-07-11)
memory and registers\CacheMemory\Memory.vhd (2411, 2017-07-11)
memory and registers\CacheMemory\MissHitLogic.vhd (801, 2017-07-11)
memory and registers\CacheMemory\ReplacementLogic.vhd (883, 2017-07-11)
... ...

# SAYEH Design and implementation of a small modular processor, called SAYEH (Simple Architecture, Yet Enough Hardware) which contains [Controller](http://whatis.techtarget.com/definition/controller) and [Datapath](https://en.wikipedia.org/wiki/Datapath) SAYEH Extension : 2-way set associative cache with write-through policy. Here see the instruction set and datapath and the state machine that designed for the Control Unit

  

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