Median_Filter
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：18835KB
下载次数：6
上传日期：2019-03-17 17:11:17
上 传 者：
柚子黑贤
说明： 基于Vivado HLS的Sobel图象边缘检测 ，语言是Verilog，欢迎广大朋友前来交流
(Sobel image detection)
文件列表:
Median_Filter (0, 2019-01-18)
Median_Filter\archive_project_summary.txt (8771, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\activehdl (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\ies (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\modelsim (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\questa (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\riviera (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\vcs (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\compile_simlib\xcelium (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\ip (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.cache\ip\2017.4 (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\gui_handlers (2).wdf (1012, 2017-11-18)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\gui_handlers.wdf (4902, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\java_command_handlers (2).wdf (377, 2017-11-18)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\java_command_handlers.wdf (1846, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\project.wpc (122, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\synthesis.wdf (5412, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\synthesis_details.wdf (100, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\webtalk_pa (2).xml (2186, 2017-11-18)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\webtalk_pa.xml (5286, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.cache\wt\xsim.wdf (239, 2017-08-27)
Median_Filter\Uart_Gray_Median_Filter.hw (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.hw\hw_1 (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.hw\hw_1\hw.xml (1234, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.hw\hw_1\wave (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.hw\Uart_Gray_Median_Filter.lpr (343, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.ipdefs (0, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\clk_VGA (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\clk_VGA\clk_VGA.veo (3694, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\clk_VGA\clk_VGA_stub.v (1246, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\clk_VGA\clk_VGA_stub.vhdl (1218, 2018-11-23)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\Shift_RAM_3X3_8bit (0, 2019-01-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\Shift_RAM_3X3_8bit\Shift_RAM_3X3_8bit.veo (3020, 2017-11-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\Shift_RAM_3X3_8bit\Shift_RAM_3X3_8bit.vho (3264, 2017-11-18)
Median_Filter\Uart_Gray_Median_Filter.ip_user_files\ip\Uart_VGA_RAM (0, 2019-01-18)
... ...
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
近期下载者：
相关文件：
收藏者：