pj_gtx
所属分类：VHDL/FPGA/Verilog
开发工具：Verilog
文件大小：4189KB
下载次数：12
上传日期：2019-03-25 21:40:10
上 传 者：
麒零丿空
说明： 利用高速口GTX进行快速的数据传输，包括接受和发送模块，用途广泛
(The use of high-speed port GTX for fast data transmission, including receiving and sending modules, has a wide range of uses.)
文件列表:
pj_gtx\gtx\par\gtx_0619_1.cdc (22099, 2018-12-11)
pj_gtx\gtx\par\iseconfig\top_gtx.projectmgr (8379, 2018-12-13)
pj_gtx\gtx\par\iseconfig\top_gtx.xreport (20566, 2018-12-13)
pj_gtx\gtx\par\loopback\top_gtx.bit (11443722, 2018-06-20)
pj_gtx\gtx\par\ok_ver\top_gtx.bit (11443722, 2018-06-20)
pj_gtx\gtx\par\pa.fromNetlist.tcl (890, 2018-06-19)
pj_gtx\gtx\par\par_usage_statistics.html (4012, 2018-12-13)
pj_gtx\gtx\par\planAhead.ngc2edif.log (4289, 2018-06-19)
pj_gtx\gtx\par\planAhead_pid3484.debug (3788, 2018-06-19)
pj_gtx\gtx\par\planAhead_pid3544.debug (3790, 2018-06-20)
pj_gtx\gtx\par\planAhead_pid6836.debug (3788, 2018-06-17)
pj_gtx\gtx\par\top_gtx.bgn (9628, 2018-12-13)
pj_gtx\gtx\par\top_gtx.bit (11443722, 2018-12-13)
pj_gtx\gtx\par\top_gtx.bld (3272, 2018-12-13)
pj_gtx\gtx\par\top_gtx.cmd_log (2004, 2018-12-13)
pj_gtx\gtx\par\top_gtx.cpj (48461, 2018-06-20)
pj_gtx\gtx\par\top_gtx.drc (1675, 2018-12-13)
pj_gtx\gtx\par\top_gtx.gise (13353, 2018-12-13)
pj_gtx\gtx\par\top_gtx.lso (6, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ncd (819530, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ngc (455477, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ngd (1804861, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ngr (531526, 2018-12-13)
pj_gtx\gtx\par\top_gtx.pad (37200, 2018-12-13)
pj_gtx\gtx\par\top_gtx.par (20314, 2018-12-13)
pj_gtx\gtx\par\top_gtx.pcf (318132, 2018-12-13)
pj_gtx\gtx\par\top_gtx.prj (1571, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ptwx (22093, 2018-12-13)
pj_gtx\gtx\par\top_gtx.stx (0, 2018-12-13)
pj_gtx\gtx\par\top_gtx.syr (147247, 2018-12-13)
pj_gtx\gtx\par\top_gtx.twr (269107, 2018-12-13)
pj_gtx\gtx\par\top_gtx.twx (298290, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ucf (5338, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ucf.bak (5420, 2018-06-20)
pj_gtx\gtx\par\top_gtx.unroutes (355, 2018-12-13)
pj_gtx\gtx\par\top_gtx.ut (742, 2018-12-13)
pj_gtx\gtx\par\top_gtx.xise (42733, 2018-11-27)
pj_gtx\gtx\par\top_gtx.xpi (46, 2018-12-13)
pj_gtx\gtx\par\top_gtx.xst (1130, 2018-12-13)
pj_gtx\gtx\par\top_gtx_bitgen.xwbt (282, 2018-12-13)
... ...
The following files were generated for 'icon_pro' in directory
C:\Users\cheerchips_liyu\Desktop\pj_gtx\gtx\par\_ngo\cs_icon_pro\
XCO file generator:
Generate an XCO file for compatibility with legacy flows.
* icon_pro.xco
Creates an implementation netlist:
Creates an implementation netlist for the IP.
* icon_pro.ngc
* icon_pro.ucf
* icon_pro.vhd
* icon_pro.vho
Creates an HDL instantiation template:
Creates an HDL instantiation template for the IP.
* icon_pro.vho
Generate ISE metadata:
Create a metadata file for use when including this core in ISE designs
* icon_pro_xmdf.tcl
Generate ISE subproject:
Create an ISE subproject for use when including this core in ISE designs
* icon_pro.gise
* icon_pro.xise
Deliver Readme:
Readme file for the IP.
* icon_pro_readme.txt
Generate FLIST file:
Text file listing all of the output files produced when a customized core was
generated in the CORE Generator.
* icon_pro_flist.txt
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
近期下载者：
相关文件：
收藏者：