veye_mipi
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：28653KB
下载次数：22
上传日期：2019-04-01 11:08:04
上 传 者：
zipray
说明： 1、 例程功能VEYE-290-LVDS模组视频接入演示。（显示设备必须支持1080p/30或1080p/25的帧率）
Veye模组—>MIA701开发板—>HDMI显示设备
2、 本例程硬件平台
MIA701-PCIE开发板，FPGA芯片：XC7A100TFGG484
3、 软件平台Vivado2018.1。
4、 附件含开发板原理图（底板+核心板）
(1. Video access demonstration of routine function VEYE-290-LVDS module. (Display devices must support 1080p/30 or 1080p/25 frame rates) Veye Module - > MIA701 Development Board - > HDMI Display Equipment 2. The hardware platform of this routine MIA701-PCIE development board, FPGA chip: XC7A100TFG484 3. Software platform Vivado 2018.1. 4. Appendix contains schematic diagram of development board (bottom + core board))
文件列表:
veye_mipi\lvds-fpga-demo (0, 2019-04-01)
veye_mipi\lvds-fpga-demo\hdmi (0, 2018-12-04)
veye_mipi\lvds-fpga-demo\hdmi\.Xil (0, 2018-11-25)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache (0, 2018-12-04)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\activehdl (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\ies (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\modelsim (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\questa (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\riviera (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\vcs (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\compile_simlib\xcelium (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip (0, 2018-12-04)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1 (0, 2018-12-04)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0.logs (0, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0.logs\runme.log (126907, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0 (0, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\004a3ce387a078e0.xci (398339, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\stats.txt (84, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\u_ila_0.dcp (688605, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\u_ila_0_sim_netlist.v (1616052, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\u_ila_0_sim_netlist.vhdl (3477356, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\u_ila_0_stub.v (1481, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\004a3ce387a078e0\u_ila_0_stub.vhdl (1679, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571.logs (0, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571.logs\runme.log (21344, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571 (0, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\015dbf4da2992571.xci (10067, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\lvds17.dcp (13587, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\lvds17_sim_netlist.v (13857, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\lvds17_sim_netlist.vhdl (15442, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\lvds17_stub.v (1658, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\015dbf4da2992571\lvds17_stub.vhdl (1722, 2018-11-29)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b.logs (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b.logs\runme.log (22218, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b (0, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b\07f7f9a804c2b66b.xci (37783, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b\clk_wiz_0.dcp (9534, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b\clk_wiz_0_sim_netlist.v (7663, 2018-11-20)
veye_mipi\lvds-fpga-demo\hdmi\hdmi.cache\ip\2018.1\07f7f9a804c2b66b\clk_wiz_0_sim_netlist.vhdl (7713, 2018-11-20)
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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